[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/19665

to look at the new patch set (#4).

Change subject: soc/intel/common: Add Intel PCIe common code
......................................................................

soc/intel/common: Add Intel PCIe common code

Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.

Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
A src/soc/intel/common/block/pcie/Kconfig
A src/soc/intel/common/block/pcie/Makefile.inc
A src/soc/intel/common/block/pcie/pcie.c
3 files changed, 161 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19665/4
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>