[coreboot-gerrit] Change in coreboot[master]: include/device: Add pci ids for Intel GLK

[Hannah Williams (Code Review)]

Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/19686 )

Change subject: include/device: Add pci ids for Intel GLK
......................................................................

include/device: Add pci ids for Intel GLK

Change-Id: Ifbca20a0c38cc1fb8ee4b4e336d59e834fcaf57a
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/include/device/pci_ids.h
1 file changed, 25 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19686/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5a2e1b2..1dabccc 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2672,6 +2672,7 @@
 #define PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM		0x9d58
 #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM		0x9d56
 #define PCI_DEVICE_ID_INTEL_APL_LPC		0x5ae8
+#define PCI_DEVICE_ID_INTEL_GLK_LPC		0x31e8
 
 /* Intel PCIE device ids  */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1		0x9d10
@@ -2738,11 +2739,13 @@
 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA		0x9d07
 #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA		0x282a
 #define PCI_DEVICE_ID_INTEL_APL_SATA		0x5ae0
+#define PCI_DEVICE_ID_INTEL_GLK_SATA		0x31e3
 
 /* Intel PMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC		0x9d21
 #define PCI_DEVICE_ID_INTEL_KBP_H_PMC		0xa121
 #define PCI_DEVICE_ID_INTEL_APL_PMC		0x5a94
+#define PCI_DEVICE_ID_INTEL_GLK_PMC		0x3194
 
 /* Intel I2C device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_I2C0		0x9d60
@@ -2759,6 +2762,14 @@
 #define PCI_DEVICE_ID_INTEL_APL_I2C5		0x5ab6
 #define PCI_DEVICE_ID_INTEL_APL_I2C6		0x5ab8
 #define PCI_DEVICE_ID_INTEL_APL_I2C7		0x5aba
+#define PCI_DEVICE_ID_INTEL_GLK_I2C0		0x31ac
+#define PCI_DEVICE_ID_INTEL_GLK_I2C1		0x31ae
+#define PCI_DEVICE_ID_INTEL_GLK_I2C2		0x31b0
+#define PCI_DEVICE_ID_INTEL_GLK_I2C3		0x31b2
+#define PCI_DEVICE_ID_INTEL_GLK_I2C4		0x31b4
+#define PCI_DEVICE_ID_INTEL_GLK_I2C5		0x31b6
+#define PCI_DEVICE_ID_INTEL_GLK_I2C6		0x31b8
+#define PCI_DEVICE_ID_INTEL_GLK_I2C7		0x31ba
 
 /* Intel UART device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_UART0		0x9d27
@@ -2771,6 +2782,10 @@
 #define PCI_DEVICE_ID_INTEL_APL_UART1		0x5abe
 #define PCI_DEVICE_ID_INTEL_APL_UART2		0x5ac0
 #define PCI_DEVICE_ID_INTEL_APL_UART3		0x5aee
+#define PCI_DEVICE_ID_INTEL_GLK_UART0		0x31bc
+#define PCI_DEVICE_ID_INTEL_GLK_UART1		0x31be
+#define PCI_DEVICE_ID_INTEL_GLK_UART2		0x31c0
+#define PCI_DEVICE_ID_INTEL_GLK_UART3		0x31ee
 
 /* Intel SPI device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_SPI1		0x9d24
@@ -2780,6 +2795,9 @@
 #define PCI_DEVICE_ID_INTEL_APL_SPI1		0x5ac4
 #define PCI_DEVICE_ID_INTEL_APL_SPI2		0x5ac6
 #define PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI		0x5a96
+#define PCI_DEVICE_ID_INTEL_GLK_SPI0		0x31c2
+#define PCI_DEVICE_ID_INTEL_GLK_SPI1		0x31c4
+#define PCI_DEVICE_ID_INTEL_GLK_SPI2		0x31c6
 
 /* Intel IGD device Ids */
 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM		0x1906
@@ -2794,9 +2812,11 @@
 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM		0x591B
 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505		0x5a84
 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500		0x5a85
+#define PCI_DEVICE_ID_INTEL_GLK_IGD			0x3184
 
 /* Intel Northbridge Ids */
 #define PCI_DEVICE_ID_INTEL_APL_NB		0x5af0
+#define PCI_DEVICE_ID_INTEL_GLK			0x31f0
 
 /* Intel SMBUS device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS		0x9d23
@@ -2807,18 +2827,23 @@
 #define PCI_DEVICE_ID_INTEL_GLK_XHCI		0x31a8
 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI		0x9d2f
 #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI		0xa12f
+#define PCI_DEVICE_ID_INTEL_GLK_XHCI		0x31a8
 
 /* Intel P2SB device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_P2SB		0x5a92
+#define PCI_DEVICE_ID_INTEL_GLK_P2SB		0x3192
 
 /* Intel SRAM device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SRAM		0x5aec
+#define PCI_DEVICE_ID_INTEL_GLK_SRAM		0x31ec
 
 /* Intel AUDIO device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_AUDIO		0x5a98
+#define PCI_DEVICE_ID_INTEL_GLK_AUDIO		0x3198
 
 /* Intel HECI/ME device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_CSE0		0x5a9a
+#define PCI_DEVICE_ID_INTEL_GLK_CSE0		0x319a
 
 /* Intel XDCI device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_XDCI		0x5aaa

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifbca20a0c38cc1fb8ee4b4e336d59e834fcaf57a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>