[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add option to enable/disable EIST

[Subrata Banik (Code Review)]

Hello Aaron Durbin, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/19676

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Add option to enable/disable EIST
......................................................................

soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
4 files changed, 19 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19676/2
-- 
To view, visit https://review.coreboot.org/19676
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>