[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 )

Change subject: soc/intel/common: Add Intel PCIe common code
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Patch Set 2:

(4 comments)

https://review.coreboot.org/#/c/19665/1/src/soc/intel/common/block/pcie/pcie.c
File src/soc/intel/common/block/pcie/pcie.c:

PS1, Line 35: 
> can you use macro, i guess this is bit definition
Done.Revised to use macro for value representing cache line size.


PS1, Line 40: date_config16(d
> why not use kconfig option for more debug pcie
Done


PS1, Line 61: 
> is that fix for all socs
Yes,for existing SOCs.Revised implementation and moved it to soc/Kconfig to provide provision to change,if it changes for upcoming SOCs.


PS1, Line 73: 	.read_resources		
> remove if not needed
Done


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Gerrit-MessageType: comment
Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
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