[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Add romstage timestamps

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19678 )

Change subject: nb/intel/gm45: Add romstage timestamps
......................................................................

nb/intel/gm45: Add romstage timestamps

Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/t400/romstage.c
M src/mainboard/lenovo/x200/romstage.c
M src/mainboard/roda/rk9/romstage.c
M src/northbridge/intel/gm45/raminit.c
4 files changed, 16 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19678/1

diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 31a80a4..1a5c17c 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -31,6 +31,7 @@
 #include <console/console.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
+#include <timestamp.h>
 #include "dock.h"
 #include "gpio.h"
 
@@ -60,6 +61,9 @@
 	int cbmem_initted;
 	u16 reg16;
 
+	timestamp_init(timestamp_get());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 49c5528..02f7116 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -32,6 +32,7 @@
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include "gpio.h"
+#include <timestamp.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define MCH_DEV PCI_DEV(0, 0, 0)
@@ -58,6 +59,9 @@
 	int cbmem_initted;
 	u16 reg16;
 
+	timestamp_init(timestamp_get());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 720f628..9a8e34b 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -32,6 +32,7 @@
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <superio/smsc/lpc47n227/lpc47n227.h>
+#include <timestamp.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
@@ -124,6 +125,9 @@
 	int cbmem_initted;
 	u16 reg16;
 
+	timestamp_init(timestamp_get());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 30e9297..d2da3b0 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <delay.h>
+#include <timestamp.h>
 #include "gm45.h"
 #include "chip.h"
 
@@ -1713,6 +1714,7 @@
 	int ch;
 	u8 reg8;
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
 
 	/* Wait for some bit, maybe TXT clear. */
 	if (sysinfo->txt_enabled) {
@@ -1825,4 +1827,6 @@
 
 	raminit_thermal(sysinfo);
 	init_igd(sysinfo);
+
+	timestamp_add_now(TS_AFTER_INITRAM);
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>