[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19666 )

Change subject: soc/intel/skylake: Use Intel PCIe common code
......................................................................

soc/intel/skylake: Use Intel PCIe common code

Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
2 files changed, 1 insertion(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19666/2

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index dbe9684..8f047ac 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -54,6 +54,7 @@
 	select SOC_INTEL_COMMON_BLOCK_GSPI
 	select SOC_INTEL_COMMON_BLOCK_ITSS
 	select SOC_INTEL_COMMON_BLOCK_LPSS
+	select SOC_INTEL_COMMON_BLOCK_PCIE
 	select SOC_INTEL_COMMON_BLOCK_PCR
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index d25332c..e0c80f9 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -66,7 +66,6 @@
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
 ramstage-y += pch.c
-ramstage-y += pcie.c
 ramstage-y += pei_data.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>