[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
Aamir Bohra (Code Review)
gerrit at coreboot.org
Thu May 11 22:17:57 CEST 2017
Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19665 )
Change subject: soc/intel/common: Add Intel PCIe common code
......................................................................
soc/intel/common: Add Intel PCIe common code
Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
A src/soc/intel/common/block/pcie/Kconfig
A src/soc/intel/common/block/pcie/Makefile.inc
A src/soc/intel/common/block/pcie/pcie.c
3 files changed, 147 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19665/1
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig
new file mode 100644
index 0000000..d494411
--- /dev/null
+++ b/src/soc/intel/common/block/pcie/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_PCIE
+ bool
+ help
+ Intel Processor common PCIE support
diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc
new file mode 100644
index 0000000..ac311a7
--- /dev/null
+++ b/src/soc/intel/common/block/pcie/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
new file mode 100644
index 0000000..e2fe169
--- /dev/null
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+
+static void pch_pcie_init(struct device *dev)
+{
+ u16 reg16;
+
+ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+
+ /* Enable SERR */
+ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
+
+ /* Enable Bus Master */
+ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* Set Cache Line Size to 0x10 */
+ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10);
+
+ /* disable parity error response, enable ISA */
+ pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~(1), 1<<2);
+
+#ifdef EVEN_MORE_DEBUG
+ printk(BIOS_SPEW, " MBL = 0x%08x\n",
+ pci_read_config32(dev, PCI_MEMORY_BASE));
+ printk(BIOS_SPEW, " PMBL = 0x%08x\n",
+ pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
+ printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
+ pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
+ printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
+ pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
+#endif
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, PCI_STATUS);
+ pci_write_config16(dev, PCI_STATUS, reg16);
+ reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
+ pci_write_config16(dev, PCI_SEC_STATUS, reg16);
+}
+
+static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
+{
+ /* Set max snoop and non-snoop latency for the SOC */
+ pci_write_config32(dev, offset, 0x10031003);
+}
+
+static struct pci_operations pcie_ops = {
+ .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pch_pcie_init,
+ .enable = NULL,
+ .scan_bus = pciexp_scan_bridge,
+ .ops_pci = &pcie_ops,
+};
+
+static const unsigned short pcie_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
+ PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23,
+ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24,
+ 0
+};
+
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pcie_device_ids,
+};
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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