[coreboot-gerrit] Change in coreboot[master]: [WIP]src/sb/bd82x6x: Use default DxxIP and DxxIR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Thu May 11 15:11:51 CEST 2017
Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19662 )
Change subject: [WIP]src/sb/bd82x6x: Use default DxxIP and DxxIR
......................................................................
[WIP]src/sb/bd82x6x: Use default DxxIP and DxxIR
The defaults only use PIRQ A, B, C and D for PCI devices which does
not conflict with PIRQ needed on some chromebooks needed for trackpad
and/or light sensor.
Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
D src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/butterfly/dsdt.asl
M src/mainboard/google/butterfly/romstage.c
D src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/link/dsdt.asl
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/dsdt.asl
M src/mainboard/google/parrot/romstage.c
D src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/stout/dsdt.asl
M src/mainboard/google/stout/romstage.c
D src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
M src/mainboard/samsung/lumpy/dsdt.asl
M src/mainboard/samsung/lumpy/romstage.c
D src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
M src/mainboard/samsung/stumpy/dsdt.asl
M src/mainboard/samsung/stumpy/romstage.c
M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
D src/southbridge/intel/bd82x6x/early_rcba.c
19 files changed, 36 insertions(+), 635 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/19662/1
diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index b837442..0000000
--- a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 3e13a41..5a0b6c7 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -44,7 +44,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 70916d5..2f1aed1 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -57,43 +57,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P2IP ETH0 INTB -> PIRQF
- * D28IP_P3IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6aebd13..0000000
--- a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 19 },
- Package() { 0x001cffff, 1, 0, 20 },
- Package() { 0x001cffff, 2, 0, 17 },
- Package() { 0x001cffff, 3, 0, 18 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 },
- Package() { 0x001fffff, 1, 0, 23 },
- Package() { 0x001fffff, 2, 0, 16 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
index da4587d..f69c613 100644
--- a/src/mainboard/google/link/dsdt.asl
+++ b/src/mainboard/google/link/dsdt.asl
@@ -44,7 +44,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 733aa30..1a40bc5 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -70,40 +70,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P3IP WLAN INTA -> PIRQB
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * TRACKPAD -> PIRQE (Edge Triggered)
- * TOUCHSCREEN -> PIRQG (Edge Triggered)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 3e13a41..5a0b6c7 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -44,7 +44,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index d9f2f8f..cc25c2a 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -55,44 +55,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P2IP WLAN INTA -> PIRQB
- * D28IP_P3IP ETH0 INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQE
- * D26IP_E2P EHCI2 INTA -> PIRQE
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQH
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- *
- * Trackpad DVT PIRQA (16)
- * Trackpad DVT PIRQE (20)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
- (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
- (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
- (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 64ec07f..0000000
--- a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 19 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 19 },
- Package() { 0x001cffff, 1, 0, 20 },
- Package() { 0x001cffff, 2, 0, 17 },
- Package() { 0x001cffff, 3, 0, 18 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 },
- Package() { 0x001fffff, 1, 0, 23 },
- Package() { 0x001fffff, 2, 0, 16 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 3a822ed..e70f986 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -44,7 +44,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index d054b39..7a30e3c 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -61,44 +61,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D20IP_XHCI XHCI INTA -> PIRQD (MSI)
- * D26IP_E2P EHCI #2 INTA -> PIRQF
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- * D28IP_P2IP WLAN INTA -> PIRQD
- * D28IP_P3IP Card Reader INTB -> PIRQE
- * D28IP_P6IP LAN INTC -> PIRQB
- * D29IP_E1P EHCI #1 INTA -> PIRQD
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
- (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
- (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
- (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
- RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
- DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 0b93cd6..0000000
--- a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 18 },
- Package() { 0x001cffff, 2, 0, 19 },
- Package() { 0x001cffff, 3, 0, 16 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 17 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 22 },
- Package() { 0x001fffff, 2, 0, 23 },
- Package() { 0x001fffff, 3, 0, 17 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
- })
- }
-}
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 28b0c1b..35826ce 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -46,7 +46,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 2a4bb4c..ab652c6 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -67,42 +67,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P4IP ETH0 INTB -> PIRQC (MSI)
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQB
- * D31IP_SIP SATA INTA -> PIRQA (MSI)
- * D31IP_SMIP SMBUS INTC -> PIRQH
- * D31IP_TTIP THRT INTB -> PIRQG
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- *
- * LIGHTSENSOR -> PIRQE (Edge Triggered)
- * TRACKPAD -> PIRQF (Edge Triggered)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index fb9d5ad..0000000
--- a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 18 },
- Package() { 0x001cffff, 2, 0, 19 },
- Package() { 0x001cffff, 3, 0, 20 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 20 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 21 },
- Package() { 0x001fffff, 1, 0, 22 },
- Package() { 0x001fffff, 2, 0, 23 },
- Package() { 0x001fffff, 3, 0, 16 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 3e13a41..5a0b6c7 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -44,7 +44,7 @@
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include "acpi/sandybridge_pci_irqs.asl"
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index c4df1e7..dcf413c 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -79,39 +79,6 @@
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P4IP ETH0 INTB -> PIRQC
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQE
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQH
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
index 0e6f960..776f316 100644
--- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
@@ -14,64 +14,66 @@
* GNU General Public License for more details.
*/
-/* PCI Interrupt Routing */
+/* Default PCI Interrupt Routing based on default DxxIP and DxxIR */
Method(_PRT)
{
If (PICM) {
Return (Package() {
- /* Onboard graphics (IGD) 0:2.0 */
- Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
/* PCI Express Graphics (PEG) 0:1.0 */
Package() { 0x0001ffff, 0, 0, 16 },/* GFX PCIe INTA -> PIRQA (MSI) */
Package() { 0x0001ffff, 0, 0, 17 },/* GFX PCIe INTB -> PIRQB (MSI) */
Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */
Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */
+ /* Onboard graphics (IGD) 0:2.0 */
+ Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
/* XHCI 0:14.0 (ivy only) */
- Package() { 0x0014ffff, 0, 0, 19 },
+ Package() { 0x0014ffff, 0, 0, 16 }, /* D20 INTA -> PIRQA */
+ /* MEI 0:16.0 */
+ Package() { 0x0016ffff, 0, 0, 16 },/* D22 INTA -> PIRQA */
+ /* GBE 0:19.0 */
+ Package() { 0x0019ffff, 0, 0, 16 },/* D25 INTA -> PIRQA */
+ /* EHCI #2 0:1a.0 */
+ Package() { 0x001affff, 0, 0, 16 },/* D26IP_E2P EHCI2 INTA -> PIRQA */
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
/* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */
- Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */
- Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */
- Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */
+ Package() { 0x001cffff, 0, 0, 16 },/* D28IP_P1IP PCIe INTA -> PIRQA */
+ Package() { 0x001cffff, 1, 0, 17 },/* D28IP_P2IP PCIe INTB -> PIRQB */
+ Package() { 0x001cffff, 2, 0, 18 },/* D28IP_P3IP PCIe INTC -> PIRQC */
+ Package() { 0x001cffff, 3, 0, 19 },/* D28IP_P3IP PCIe INTD -> PIRQD */
/* EHCI #1 0:1d.0 */
- Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */
- /* EHCI #2 0:1a.0 */
- Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */
+ Package() { 0x001dffff, 0, 0, 16 },/* D29IP_E1P EHCI1 INTA -> PIRQA */
/* LPC devices 0:1f.0 */
- Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
- Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
- Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
- Package() { 0x001fffff, 3, 0, 18 },
+ Package() { 0x001fffff, 1, 0, 17 }, /* D31IP_SMIP SMBUS INTB -> PIRQB */
})
} Else {
Return (Package() {
- /* Onboard graphics (IGD) 0:2.0 */
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* PCI Express Graphics (PEG) 0:1.0 */
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* Onboard graphics (IGD) 0:2.0 */
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* XHCI 0:14.0 (ivy only) */
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* GBE 0:16.0 */
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* GBE 0:19.0 */
+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* EHCI #2 0:1a.0 */
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
/* EHCI #1 0:1d.0 */
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- /* EHCI #2 0:1a.0 */
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* LPC device 0:1f.0 */
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
})
}
}
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
deleted file mode 100644
index eeecb5f..0000000
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- * Copyright (C) 2014 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include "pch.h"
-#include "northbridge/intel/sandybridge/sandybridge.h"
-
-void
-southbridge_configure_default_intmap(void)
-{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP SLOT1 INTA -> PIRQB
- * D28IP_P2IP SLOT2 INTB -> PIRQF
- * D28IP_P3IP SLOT3 INTC -> PIRQD
- * D28IP_P5IP SLOT5 INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
-
- */
-
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-}
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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