[coreboot-gerrit] Change in coreboot[master]: mainboard: Add ASRock G41C-GS

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 )

Change subject: mainboard: Add ASRock G41C-GS
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Patch Set 11:

(4 comments)

https://review.coreboot.org/#/c/18993/6/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
File src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl:

PS6, Line 40: 			Package() { 0x001fffff, 0, 0, 0x12 },
            : 			Package() { 0x001fffff, 1, 0, 0x13 },
            : 			Package() { 0x001fffff, 2, 0, 0x11 },
            : 			Package() { 0x001fffff, 3, 0, 0x10 },
> Ping.
I see, so by default both SATA and SMBUS share the same interrupt pin.


https://review.coreboot.org/#/c/18993/7/src/mainboard/asrock/g41c-gs/romstage.c
File src/mainboard/asrock/g41c-gs/romstage.c:

Line 51: 
> Ping.
from datasheet, D30IP sets PINs for "AC ‘97 Audio Pin (AAIP)" default Pin A and "AC ‘97 Modem Pin (AMIP)", default PIN B, with RO LPC not using pin set by lower bits. PCI bridge PIN (unused) is RO and in lower bits of D31IP.

I guess it could be left untoched...


https://review.coreboot.org/#/c/18993/10/src/mainboard/asrock/g41c-gs/romstage.c
File src/mainboard/asrock/g41c-gs/romstage.c:

Line 69: 	RCBA32(GCS) = 0x00700464;
> Please sanitize (if it's from a dump, some reserved bits set might
ok


Line 72: 	RCBA32(CG) = 0x00000001;
> Does the PCIe x1 slot work with this?
I'd have to test this. I should have a PCIe 16x to 1x riser  soon (no pcie device with right form factor here...)


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Gerrit-MessageType: comment
Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Gerrit-PatchSet: 11
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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