[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob

[Caesar Wang (Code Review)]

Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )

Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................


Patch Set 7:

(4 comments)

https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:

Line 349:  *    extern wave table).
> nit: Should you maybe do this as you're writing it here? You're only settin
Done


Line 360: 	 * TODO find the root cause why is the delay needed, Otherwise sometime
> Okay. Please change the comment to reflect that you don't know why the dela
Done


Line 373: 	/* Use frac mode */
> Sorry, I don't understand what you mean. According to the TRM (PLL initiali
Okay, you are right here. 
I will set 0 for DPLL_CON2. Sorry!


Line 373: 	/* Use frac mode */
> So we're enabling fractional mode here, but where are we setting the fracti
0x31f / (2 << 24) == 0.00024% of the intended rate (i.e. 22KHz)? =====> that's offset for frequency

I just confirm with the SSC owner, the best way is we set the 0 for DPLL_CON2.


-- 
To view, visit https://review.coreboot.org/19557
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: comment
Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt at rock-chips.com>
Gerrit-Reviewer: Caesar Wang <wxt at rock-chips.com>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philip Chen <philipchen at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-HasComments: Yes