[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable MTRR check

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19609 )

Change subject: soc/intel/skylake: Enable MTRR check
......................................................................

soc/intel/skylake: Enable MTRR check

Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.

BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.

Change-Id: I440405c58c470ffa338be386d84870635530a031
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/cpu.c
1 file changed, 1 insertion(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/19609/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0b1b9af..2f35635 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -523,6 +523,7 @@
 {
 	if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
 		printk(BIOS_ERR, "MTRR programming failure\n");
+	x86_mtrr_check();
 }
 
 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I440405c58c470ffa338be386d84870635530a031
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>