[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable PARALLEL_MP_AP_WORK

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19608 )

Change subject: soc/intel/skylake: Enable PARALLEL_MP_AP_WORK
......................................................................

soc/intel/skylake: Enable PARALLEL_MP_AP_WORK

With change a4b11e5c90 to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.

BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.

Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/19608/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 515de91..fba6f7f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -38,6 +38,7 @@
 	select NO_FIXED_XIP_ROM_SIZE
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
+	select PARALLEL_MP_AP_WORK
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>