[coreboot-gerrit] Change in coreboot[master]: mb/asus/p5gc-mx: Implement flawed resume from S3 support

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19602 )

Change subject: mb/asus/p5gc-mx: Implement flawed resume from S3 support
......................................................................

mb/asus/p5gc-mx: Implement flawed resume from S3 support

On s3 resume BSEL straps are not configured which require a hard reset
to work which conflicts with s3 resume. The result is that on s3
resume the cpu is run at 800MHz FSB. This however does not work with
each CPU, but it's better than no S3 support at all.

Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/asus/p5gc-mx/Kconfig
M src/mainboard/asus/p5gc-mx/devicetree.cb
M src/mainboard/asus/p5gc-mx/romstage.c
3 files changed, 14 insertions(+), 15 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/19602/1

diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
index 445d932..83001e0 100644
--- a/src/mainboard/asus/p5gc-mx/Kconfig
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -21,7 +21,6 @@
 	select CPU_INTEL_SOCKET_LGA775
 	select NORTHBRIDGE_INTEL_I945
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
-	select CHECK_SLFRCS_ON_RESUME
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627DHG
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index 824beed..a7394e0 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -116,6 +116,7 @@
 					device pnp 2e.9 on end # GPIO2-5
 					device pnp 2e.a on # ACPI
 						irq 0x70 = 0
+						irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
 					end
 					device pnp 2e.b on # HWM
 						io 0x60 = 0x290
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index efeaaec..a29478c 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -49,7 +49,7 @@
  * BSEL1 is connected with GPIO33 with inversed logic
  * BSEL2 is connected with GPIO55
  */
-static void setup_sio_gpio(u8 bsel)
+static int setup_sio_gpio(u8 bsel)
 {
 	int need_reset = 0;
 	u8 reg, old_reg;
@@ -83,13 +83,7 @@
 
 	pnp_exit_ext_func_mode(GPIO_DEV);
 
-	if (need_reset) {
-		int i = 1000;
-		while (i--)
-			outb(i & 0xff, 0x80);
-		outb(0xe, 0xcf9);
-		halt();
-	}
+	return need_reset;
 }
 
 static u8 msr_get_fsb(void)
@@ -197,7 +191,6 @@
 {
 	int s3resume = 0, boot_mode = 0;
 
-	u8 m_bsel;
 	u8 c_bsel = msr_get_fsb();
 
 	timestamp_init(get_initial_timestamp());
@@ -209,8 +202,6 @@
 	ich7_enable_lpc();
 
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-	setup_sio_gpio(c_bsel);
 
 	/* Set up the console */
 	console_init();
@@ -228,11 +219,19 @@
 	 */
 	i945_early_initialization();
 
-	m_bsel = MCHBAR32(CLKCFG) & 7;
-	printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel);
-
 	s3resume = southbridge_detect_s3_resume();
 
+	/*
+	 * Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
+	 * Some CPU accept this others don't.
+	 */
+	if (!s3resume && setup_sio_gpio(c_bsel)) {
+		printk(BIOS_DEBUG,
+			"Needs reset to configure CPU BSEL straps\n");
+		outb(0xe, 0xcf9);
+		halt();
+	}
+
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>