[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable SATA ports

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19553 )

Change subject: soc/intel/skylake: Enable SATA ports
......................................................................


soc/intel/skylake: Enable SATA ports

The current implementation is incorrect and is
actually disabling the ports.  Fixes that.

BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
     SATA SSD.

Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen at chromium.org>
Reviewed-on: https://review.coreboot.org/19553
Reviewed-by: Furquan Shaikh <furquan at google.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
M src/soc/intel/skylake/sata.c
1 file changed, 6 insertions(+), 4 deletions(-)

Approvals:
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c
index c110436..277d6da 100644
--- a/src/soc/intel/skylake/sata.c
+++ b/src/soc/intel/skylake/sata.c
@@ -40,14 +40,16 @@
 static void sata_final(device_t dev)
 {
 	void *ahcibar = get_ahci_bar();
-	u8 port_impl;
+	u32 port_impl, temp;
 
 	dev = PCH_DEV_SATA;
 	/* Read Ports Implemented (GHC_PI) */
-	port_impl = read32(ahcibar + 0x0c);
-	port_impl = ~port_impl & 0x07;
+	port_impl = read32(ahcibar + 0x0c) & 0x07;
 	/* Port enable */
-	pci_write_config8(dev, 0x92, port_impl);
+	temp = pci_read_config32(dev, 0x92);
+	temp |= port_impl;
+	pci_write_config32(dev, 0x92, temp);
+
 }
 
 static struct device_operations sata_ops = {

-- 
To view, visit https://review.coreboot.org/19553
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: merged
Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>