[coreboot-gerrit] Change in coreboot[master]: mainboard/google/sand: Update DPTF parameters provided from ...

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19538 )

Change subject: mainboard/google/sand: Update DPTF parameters provided from thermal team
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mainboard/google/sand: Update DPTF parameters provided from thermal team

Update the DPTF parameters based on thermal test result.

1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
   CPU  passive point:83,  critial point:99
   TSR0 passive point:60,  critial point:70
   TSR1 passive point:50,  critial point:90
   TSR2 passive point:77,  critial point:90

2. Update PL1/PL2 Min Power Limit/Max Power Limit
   Set PL1 min to 4W, max to 12W, and step size to 0.2W

3. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 5secs
   Change CPU Effect on Temp Sensor 0 sample rate to 60secs
   The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
   Change Charger Effect on Temp Sensor 2 sample rate to 30secs
   Change CPU Effect on Temp Sensor 2 sample rate to 120secs

BUG=None
TEST=build and boot on electro dut

Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh at quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl
1 file changed, 70 insertions(+), 2 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl
index fe4bf01..e90b159 100644
--- a/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl
@@ -14,5 +14,73 @@
  * GNU General Public License for more details.
  */
 
-/* Use the one from baseboard for now until the real testing is done. */
-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE	83
+#define DPTF_CPU_CRITICAL	99
+#define DPTF_CPU_ACTIVE_AC0	90
+#define DPTF_CPU_ACTIVE_AC1	80
+#define DPTF_CPU_ACTIVE_AC2	70
+#define DPTF_CPU_ACTIVE_AC3	60
+#define DPTF_CPU_ACTIVE_AC4	50
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Battery"
+#define DPTF_TSR0_PASSIVE	60
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Ambient"
+#define DPTF_TSR1_PASSIVE	50
+#define DPTF_TSR1_CRITICAL	90
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Charger"
+#define DPTF_TSR2_PASSIVE	77
+#define DPTF_TSR2_CRITICAL	90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		4000,	/* PowerLimitMinimum */
+		12000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Katherine Hsieh <Katherine.Hsieh at quantatw.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>