[coreboot-gerrit] Change in coreboot[master]: mainboard/google/reef: Config needed GPIO for pull-up WA

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded a new change for review. ( https://review.coreboot.org/19577 )

Change subject: mainboard/google/reef: Config needed GPIO for pull-up WA
......................................................................

mainboard/google/reef: Config needed GPIO for pull-up WA

This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.

For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down 
on mainboard, change internal pull up to none.

BUG=b.37998248
TEST=Boot up into OS and enter s0ix.

Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/google/reef/variants/baseboard/gpio.c
1 file changed, 13 insertions(+), 13 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19577/8

diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 9155e66..5aa9f77 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -31,15 +31,15 @@
 
 	/* EMMC interface */
 	PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */
-	PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */
-	PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */
-	PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */
-	PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */
-	PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */
-	PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */
-	PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */
-	PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */
-	PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D0 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D1 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D2 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D3 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D4 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D5 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D6 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D7 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_CMD */
 	PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
 
 	/* SDIO -- unused. */
@@ -245,8 +245,8 @@
 	PAD_CFG_GPI(GPIO_98, UP_20K, DEEP),				/* FST_SPI_CS1_B -- unused */
 	PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_MOSI_IO0 */
 	PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_MISO_IO1 */
-	PAD_CFG_GPI(GPIO_101, UP_20K, DEEP),				/* FST_IO2 -- MEM_CONFIG0 */
-	PAD_CFG_GPI(GPIO_102, UP_20K, DEEP),				/* FST_IO3 -- MEM_CONFIG1 */
+	PAD_CFG_GPI(GPIO_101, NONE, DEEP),				/* FST_IO2 -- MEM_CONFIG0 */
+	PAD_CFG_GPI(GPIO_102, NONE, DEEP),				/* FST_IO3 -- MEM_CONFIG1 */
 	PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE),	/* FST_SPI_CLK */
 	PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */
 	PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE),	/* FST_SPI_CS2_N */
@@ -316,7 +316,7 @@
 	PAD_CFG_GPI(GPIO_37, UP_20K, DEEP),	 /* unused */
 
 	/* LPSS_UART[0:2] */
-	PAD_CFG_GPI(GPIO_38, UP_20K, DEEP),	 /* LPSS_UART0_RXD - MEM_CONFIG2*/
+	PAD_CFG_GPI(GPIO_38, NONE, DEEP),	 /* LPSS_UART0_RXD - MEM_CONFIG2*/
 	/* Next 2 are straps. */
 	PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),	 /* LPSS_UART0_TXD - unused */
 	PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),	 /* LPSS_UART0_RTS - unused */
@@ -324,7 +324,7 @@
 	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),	 /* LPSS_UART1_RXD */
 	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),	 /* LPSS_UART1_TXD */
 	PAD_CFG_GPO(GPIO_44, 1, DEEP),	 /* GPS_RST_ODL */
-	PAD_CFG_GPI(GPIO_45, UP_20K, DEEP),	 /* LPSS_UART1_CTS - MEM_CONFIG3 */
+	PAD_CFG_GPI(GPIO_45, NONE, DEEP),	 /* LPSS_UART1_CTS - MEM_CONFIG3 */
 	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),	 /* LPSS_UART2_RXD */
 	PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */
 	PAD_CFG_GPI(GPIO_48, UP_20K, DEEP),	 /* LPSS_UART2_RTS - unused */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov at intel.com>
Gerrit-Reviewer: Freddy Paul <freddy.paul at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>