[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Provide common block fast_spi_flash_ctrlr

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19575 )

Change subject: soc/intel/common: Provide common block fast_spi_flash_ctrlr
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/19575/2/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:

Line 354: const struct spi_ctrlr fast_spi_flash_ctrlr = {
> Did we want to test that cs == 0 like the prev ->setup() routines?
Yeah, I was thinking about that too, but did not add that since we are allowing SoCs to provide bus-ctrlr mapping. I will add it back. 

Maybe we should have a config option which says SPI_FLASH_BUS and have that check? In fact that SPI_FLASH_BUS can be used within coreboot at a number of places.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Gerrit-PatchSet: 2
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Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
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