[coreboot-gerrit] Change in coreboot[master]: common/block/cse: Use CSE PCH ID from device/pci_ids.h

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19569 )

Change subject: common/block/cse: Use CSE PCH ID from device/pci_ids.h
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/19569/1/src/soc/intel/common/block/cse/cse.c
File src/soc/intel/common/block/cse/cse.c:

Line 474: 	.device			= PCI_DEVICE_ID_INTEL_APOLLOLAKE_CSE0
> You might as well put this into a device_ids list so that we can append. Un
yes Aaron, i would like to wait, i could see lots of assumption here, for an example CSE BAR address can't be common for all soc. we will address CSE common code and push SKL use patch right after I2C. That time, we will take care.

/* default window for early boot, must be at least 12 bytes in size */
#define HECI1_BASE_ADDRESS	0xfed1a000


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Gerrit-MessageType: comment
Gerrit-Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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