[coreboot-gerrit] Change in coreboot[master]: google/fizz: Enable SATA ports

[Shelley Chen (Code Review)]

Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/19553 )

Change subject: google/fizz: Enable SATA ports
......................................................................

google/fizz: Enable SATA ports

Previous implementation was incorrect and was
actually disabling the ports.

BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
     SATA SSD.

Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/soc/intel/skylake/sata.c
1 file changed, 6 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19553/1

diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c
index c110436..2027b03 100644
--- a/src/soc/intel/skylake/sata.c
+++ b/src/soc/intel/skylake/sata.c
@@ -40,14 +40,16 @@
 static void sata_final(device_t dev)
 {
 	void *ahcibar = get_ahci_bar();
-	u8 port_impl;
+	u32 port_impl;
 
 	dev = PCH_DEV_SATA;
 	/* Read Ports Implemented (GHC_PI) */
-	port_impl = read32(ahcibar + 0x0c);
-	port_impl = ~port_impl & 0x07;
+	port_impl = read32(ahcibar + 0x0c) & 0x07;
 	/* Port enable */
-	pci_write_config8(dev, 0x92, port_impl);
+	u32 temp = pci_read_config32(dev, 0x92);
+	temp |= port_impl;
+	pci_write_config32(dev, 0x92, temp);
+
 }
 
 static struct device_operations sata_ops = {

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>