[coreboot-gerrit] Change in coreboot[master]: google/gru: skip usbphy1 setup for Scarlet
Julius Werner (Code Review)
gerrit at coreboot.org
Wed May 3 21:45:58 CEST 2017
Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19489 )
Change subject: google/gru: skip usbphy1 setup for Scarlet
......................................................................
google/gru: skip usbphy1 setup for Scarlet
Board Scarlet doesn't use usbphy1.
BUG=b:37685249
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen at google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Julius Werner <jwerner at chromium.org>
---
M src/mainboard/google/gru/mainboard.c
M src/soc/rockchip/rk3399/include/soc/grf.h
2 files changed, 24 insertions(+), 32 deletions(-)
Approvals:
Julius Werner: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index b8a3e55..74c83bc 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -14,6 +14,7 @@
*
*/
+#include <assert.h>
#include <boardid.h>
#include <console/console.h>
#include <delay.h>
@@ -242,20 +243,20 @@
printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port);
}
-static void setup_usb(void)
+static void setup_usb(int port)
{
+ /* Must be PHY0 or PHY1. */
+ assert(port == 0 || port == 1);
+
/*
* A few magic PHY tuning values that improve eye diagram amplitude
* and make it extra sure we get reliable communication in firmware
* Set max ODT compensation voltage and current tuning reference.
*/
- write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
- write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
+ write32(&rk3399_grf->usbphy_ctrl[port][3], RK_CLRSETBITS(0xfff, 0x2e3));
/* Set max pre-emphasis level on PHY0 and PHY1. */
- write32(&rk3399_grf->usbphy0_ctrl[12],
- RK_CLRSETBITS(0xffff, 0xa7));
- write32(&rk3399_grf->usbphy1_ctrl[12],
+ write32(&rk3399_grf->usbphy_ctrl[port][12],
RK_CLRSETBITS(0xffff, 0xa7));
/*
@@ -267,44 +268,37 @@
* 2. Configure PHY0 and PHY1 otg-ports squelch detection
* threshold to 125mV (default is 150mV).
*/
- write32(&rk3399_grf->usbphy0_ctrl[0],
+ write32(&rk3399_grf->usbphy_ctrl[port][0],
RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13));
- write32(&rk3399_grf->usbphy1_ctrl[0],
- RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13));
- write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(3 << 0));
- write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(3 << 0));
+ write32(&rk3399_grf->usbphy_ctrl[port][13], RK_CLRBITS(3 << 0));
/*
* ODT auto compensation bypass, and set max driver
* strength only for PHY0 and PHY1 otg-port.
*/
- write32(&rk3399_grf->usbphy0_ctrl[2],
- RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
- write32(&rk3399_grf->usbphy1_ctrl[2],
+ write32(&rk3399_grf->usbphy_ctrl[port][2],
RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
/*
* ODT auto refresh bypass, and set the max bias current
* tuning reference only for PHY0 and PHY1 otg-port.
*/
- write32(&rk3399_grf->usbphy0_ctrl[3],
- RK_CLRSETBITS(0x21c, 1 << 4));
- write32(&rk3399_grf->usbphy1_ctrl[3],
+ write32(&rk3399_grf->usbphy_ctrl[port][3],
RK_CLRSETBITS(0x21c, 1 << 4));
/*
* ODT auto compensation bypass, and set default driver
* strength only for PHY0 and PHY1 host-port.
*/
- write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10));
- write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10));
+ write32(&rk3399_grf->usbphy_ctrl[port][15], RK_SETBITS(1 << 10));
/* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
- write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9));
- write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9));
+ write32(&rk3399_grf->usbphy_ctrl[port][16], RK_CLRBITS(1 << 9));
- setup_usb_otg0();
- setup_usb_otg1();
+ if (port == 0)
+ setup_usb_otg0();
+ else
+ setup_usb_otg1();
/*
* Need to power-cycle USB ports for use in firmware, since some devices
@@ -312,10 +306,8 @@
* This takes about a dozen milliseconds, so only do it in boot modes
* that have firmware UI (which one could select USB boot from).
*/
- if (display_init_required()) {
- usb_power_cycle(0);
- usb_power_cycle(1);
- }
+ if (display_init_required())
+ usb_power_cycle(port);
}
static void mainboard_init(device_t dev)
@@ -325,7 +317,9 @@
configure_emmc();
configure_codec();
configure_display();
- setup_usb();
+ setup_usb(0);
+ if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET))
+ setup_usb(1);
register_reset_to_bl31();
register_poweroff_to_bl31();
register_gpio_suspend();
diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h
index c1fd690..8e12007 100644
--- a/src/soc/rockchip/rk3399/include/soc/grf.h
+++ b/src/soc/rockchip/rk3399/include/soc/grf.h
@@ -71,10 +71,8 @@
u32 reserved10[0xc9];
u32 hsicphy_con0;
u32 reserved11[3];
- u32 usbphy0_ctrl[26];
- u32 reserved12[6];
- u32 usbphy1_ctrl[26];
- u32 reserved13[0x72f];
+ u32 usbphy_ctrl[2][26 + 6]; /* 26 PHY regs, 6 reserved padding regs */
+ u32 reserved13[0x729];
u32 soc_con9;
u32 reserved14[0x0a];
u32 soc_con20;
--
To view, visit https://review.coreboot.org/19489
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Gerrit-MessageType: merged
Gerrit-Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philip Chen <philipchen at google.com>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philip Chen <philipchen at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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