[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/early_init: Use register name

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19547 )

Change subject: nb/intel/sandybridge/early_init: Use register name
......................................................................

nb/intel/sandybridge/early_init: Use register name

Use names instead of magic values.

No functional change.

Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/early_init.c
1 file changed, 3 insertions(+), 3 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/19547/1

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 16ea29d..efe27b1 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -30,10 +30,10 @@
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+	pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+	pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
+	pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
 
 	printk(BIOS_DEBUG, " done.\n");
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>