[coreboot-gerrit] Change in coreboot[master]: fsp_broadwell_de: Switch CPU to high frequency mode

[Werner Zeh (Code Review)]

Werner Zeh has uploaded a new change for review. ( https://review.coreboot.org/19537 )

Change subject: fsp_broadwell_de: Switch CPU to high frequency mode
......................................................................

fsp_broadwell_de: Switch CPU to high frequency mode

According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.

It should not harm the operation even if FSP was successful in switching
to HFM.

Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
M src/soc/intel/fsp_broadwell_de/cpu.c
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
2 files changed, 32 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/19537/1

diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index 9d7fe98..68825a3 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -65,8 +65,38 @@
 	*parallel = 1;
 }
 
+static int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Bits 34:33 indicate how many levels are supported. */
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option. */
+	if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio. */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info Bits 15:8 give max ratio. */
+		msr = rdmsr(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	wrmsr(IA32_PERF_CTL, perf_ctl);
+}
+
 static void post_mp_init(void)
 {
+	/* Set Max Ratio */
+	set_max_ratio();
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	   start flowing. */
 	southbridge_smm_enable_smi();
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f5ea34c..6b87061 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,10 +21,12 @@
 #define MSR_IA32_PLATFORM_ID	0x17
 #define MSR_CORE_THREAD_COUNT	0x35
 #define MSR_PLATFORM_INFO	0xce
+#define IA32_PERF_CTL		0x199
 #define MSR_TURBO_RATIO_LIMIT	0x1ad
 #define MSR_IA32_MC0_STATUS	0x400
 #define MSR_PKG_POWER_SKU_UNIT	0x606
 #define MSR_PKG_POWER_LIMIT	0x610
+#define MSR_CONFIG_TDP_NOMINAL	0x648
 
 #define SMM_MCA_CAP_MSR		0x17d
 #define  SMM_CPU_SVRSTR_BIT	57

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Werner Zeh <werner.zeh at siemens.com>