[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set xtal bypass on low power idle

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19442 )

Change subject: soc/intel/skylake: Set xtal bypass on low power idle
......................................................................


soc/intel/skylake: Set xtal bypass on low power idle

When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.

With xtal being active  in S0ix state power impact is 1-2 mW.

Hence set xtal bypass bit in CIR31C for low power idle entry.

TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.

Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
Reviewed-on: https://review.coreboot.org/19442
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pmc.h
2 files changed, 9 insertions(+), 1 deletion(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index f489e4b..9cb246c 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -143,6 +143,13 @@
 		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
 	}
 
+	/* Disable XTAL shutdown qualification for low power idle. */
+	if (config->s0ix_enable) {
+		reg32 = read32(pmcbase + CIR31C);
+		reg32 |= XTALSDQDIS;
+		write32(pmcbase + CIR31C, reg32);
+	}
+
 	/* we should disable Heci1 based on the devicetree policy */
 	if (config->HeciEnabled == 0)
 		pch_disable_heci();
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 10ea6ae..4a80917 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -98,5 +98,6 @@
 #define  GPE0_DW2_SHIFT		8
 #define GBLRST_CAUSE0		0x124
 #define GBLRST_CAUSE1		0x128
-
+#define CIR31C			0x31c
+#define  XTALSDQDIS		(1 << 22)
 #endif

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rajat Jain <rajatja at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park at intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam at intel.com>