[coreboot-gerrit] Change in coreboot[master]: mainboard/google/poppy: Add support for cr50 I2C TPM
Furquan Shaikh (Code Review)
gerrit at coreboot.org
Tue May 2 00:48:46 CEST 2017
Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19518 )
Change subject: mainboard/google/poppy: Add support for cr50 I2C TPM
......................................................................
mainboard/google/poppy: Add support for cr50 I2C TPM
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/gpio.c
3 files changed, 47 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19518/1
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index ce32081..9aea338 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -22,6 +22,12 @@
string
default "variants/baseboard/devicetree.cb"
+config DRIVER_TPM_I2C_BUS
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ default 0x50
+
config DRIVER_TPM_SPI_BUS
default 0x1
@@ -56,6 +62,14 @@
int
default 8
+# Select this option to enable use of cr50 I2C TPM on poppy.
+config POPPY_USE_I2C_TPM
+ bool
+ default n
+ select I2C_TPM
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select TPM2
+
# Select this option to enable use of cr50 SPI TPM on poppy.
# This option is disabled by default.
config POPPY_USE_SPI_TPM
@@ -64,6 +78,10 @@
select MAINBOARD_HAS_SPI_TPM_CR50
select SPI_TPM
select TPM2
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 64 # GPE0_DW2_00 (GPP_E0)
config VARIANT_DIR
string
@@ -75,12 +93,5 @@
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select VBOOT_LID_SWITCH
-
-config DRIVER_TPM_SPI_BUS
- default 0x1
-
-config TPM_TIS_ACPI_INTERRUPT
- int
- default 64 # GPE0_DW2_00 (GPP_E0)
endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index d232028..4e3ffaf 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -154,7 +154,7 @@
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
- register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # H1
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera
@@ -167,6 +167,12 @@
.early_init = 1,
}"
+ # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
+ # for TPM communication before memory is up.
+ register "i2c[1]" = "{
+ .early_init = 1,
+ }"
+
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c
index fcbbb1d..2be9d0f 100644
--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c
+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c
@@ -92,6 +92,7 @@
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> NC */
PAD_CFG_NC(GPP_B14),
+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
@@ -100,6 +101,16 @@
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+#else
+ /* B15 : GSPI0_CS# ==> NC */
+ PAD_CFG_NC(GPP_B15),
+ /* B16 : GSPI0_CLK ==> NC */
+ PAD_CFG_NC(GPP_B16),
+ /* B17 : GSPI0_MISO ==> NC */
+ PAD_CFG_NC(GPP_B17),
+ /* B18 : GSPI0_MOSI ==> NC */
+ PAD_CFG_NC(GPP_B18),
+#endif
/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
@@ -147,10 +158,17 @@
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+#else
+ /* C18 : I2C1_SDA ==> NC */
+ PAD_CFG_NC(GPP_C18),
+ /* C19 : I2C1_SCL ==> NC */
+ PAD_CFG_NC(GPP_C19),
+#endif
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
@@ -353,6 +371,7 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
@@ -361,11 +380,14 @@
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+#endif
+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+#endif
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
--
To view, visit https://review.coreboot.org/19518
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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