[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
Martin Roth (Code Review)
gerrit at coreboot.org
Tue Mar 28 16:39:55 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18565 )
Change subject: soc/intel/common/block: Add Intel common systemagent support
......................................................................
soc/intel/common/block: Add Intel common systemagent support
Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Reviewed-on: https://review.coreboot.org/18565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
A src/soc/intel/common/block/include/intelblocks/systemagent.h
A src/soc/intel/common/block/systemagent/Kconfig
A src/soc/intel/common/block/systemagent/Makefile.inc
A src/soc/intel/common/block/systemagent/systemagent.c
4 files changed, 123 insertions(+), 0 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
new file mode 100644
index 0000000..77248bb
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SA_H
+#define SOC_INTEL_COMMON_BLOCK_SA_H
+
+/* Device 0:0.0 PCI configuration space */
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEXBAR_LENGTH_64MB 2
+#define PCIEXBAR_LENGTH_128MB 1
+#define PCIEXBAR_LENGTH_256MB 0
+#define PCIEXBAR_PCIEXBAREN (1 << 0)
+#define GGC 0x50
+
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+
+void bootblock_systemagent_early_init(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_SA_H */
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
new file mode 100644
index 0000000..773a56b
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -0,0 +1,26 @@
+config SOC_INTEL_COMMON_BLOCK_SA
+ bool
+ help
+ Intel Processor common System Agent support
+
+config MMCONF_BASE_ADDRESS
+ hex "PCI MMIO Base Address"
+ default 0xe0000000
+
+config SA_PCIEX_LENGTH
+ hex
+ default 0x10000000 if (PCIEX_LENGTH_256MB)
+ default 0x8000000 if (PCIEX_LENGTH_128MB)
+ default 0x4000000 if (PCIEX_LENGTH_64MB)
+ default 0x10000000
+ help
+ This option allows you to select length of PCIEX region.
+
+config PCIEX_LENGTH_256MB
+ bool "256MB"
+
+config PCIEX_LENGTH_128MB
+ bool "128MB"
+
+config PCIEX_LENGTH_64MB
+ bool "64MB"
diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc
new file mode 100644
index 0000000..75d5626
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/Makefile.inc
@@ -0,0 +1 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
new file mode 100644
index 0000000..58e2c7e
--- /dev/null
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <commonlib/helpers.h>
+#include <intelblocks/systemagent.h>
+#include <soc/pci_devs.h>
+
+void bootblock_systemagent_early_init(void)
+{
+ uint32_t reg;
+ uint8_t pciexbar_length;
+
+ /*
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB.
+ */
+ reg = 0;
+ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+
+ /* Get PCI Express Region Length */
+ switch (CONFIG_SA_PCIEX_LENGTH) {
+ case 256 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_256MB;
+ break;
+ case 128 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_128MB;
+ break;
+ case 64 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_64MB;
+ break;
+ default:
+ pciexbar_length = PCIEXBAR_LENGTH_256MB;
+ }
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
+ | PCIEXBAR_PCIEXBAREN;
+ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+
+ /*
+ * TSEG defines the base of SMM range. BIOS determines the base
+ * of TSEG memory which must be at or below Graphics base of GTT
+ * Stolen memory, hence its better to clear TSEG register early
+ * to avoid power on default non-zero value (if any).
+ */
+ pci_write_config32(SA_DEV_ROOT, TSEG, 0);
+}
+
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Gerrit-PatchSet: 20
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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