[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx: Consolidate interrupt routing
Arthur Heymans (Code Review)
gerrit at coreboot.org
Mon Mar 27 21:44:40 CEST 2017
Hello Vladimir Serbinenko,
I'd like you to do a code review. Please visit
https://review.coreboot.org/19017
to review the following change.
Change subject: sb/intel/i82801gx: Consolidate interrupt routing
......................................................................
sb/intel/i82801gx: Consolidate interrupt routing
The old code tried to make routing per-board, presumably for optimizing
IRQ balancing but instead failed at providing an error-free default.
Rewrite in unified and simplified way at the cost of minor performance hit
on very old OS.
This is set up similar to newer Intel PCH where a sane default is
provided by coreboot.
Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/apple/macbook21/Kconfig
D src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
M src/mainboard/apple/macbook21/devicetree.cb
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/asus/p5gc-mx/Kconfig
D src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
M src/mainboard/asus/p5gc-mx/devicetree.cb
M src/mainboard/getac/p470/Kconfig
M src/mainboard/getac/p470/devicetree.cb
M src/mainboard/getac/p470/romstage.c
D src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
D src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
M src/mainboard/ibase/mb899/Kconfig
D src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
M src/mainboard/ibase/mb899/devicetree.cb
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d510mo/Kconfig
D src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
M src/mainboard/intel/d510mo/devicetree.cb
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/d945gclf/Kconfig
D src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
M src/mainboard/intel/d945gclf/devicetree.cb
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/Kconfig
D src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
M src/mainboard/kontron/986lcd-m/devicetree.cb
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/Kconfig
D src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
M src/mainboard/lenovo/t60/devicetree.cb
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/Kconfig
D src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
M src/mainboard/lenovo/x60/devicetree.cb
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/roda/rk886ex/Kconfig
D src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
M src/mainboard/roda/rk886ex/devicetree.cb
M src/mainboard/roda/rk886ex/romstage.c
M src/northbridge/intel/i945/acpi/hostbridge.asl
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/x4x/acpi/hostbridge.asl
M src/northbridge/intel/x4x/early_init.c
M src/southbridge/intel/i82801gx/acpi/ich7.asl
R src/southbridge/intel/i82801gx/acpi/irq.asl
M src/southbridge/intel/i82801gx/chip.h
M src/southbridge/intel/i82801gx/early_lpc.c
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/lpc.c
57 files changed, 387 insertions(+), 1,217 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19017/1
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 7ee0e1a..b277db9 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -22,6 +22,7 @@
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select VGA
select INTEL_EDID
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 5e5facb..0000000
--- a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0001FFFF, 0, 0, 0x10 },
- Package() { 0x0002FFFF, 0, 0, 0x10 },
- Package() { 0x0007FFFF, 0, 0, 0x10 },
- Package() { 0x001BFFFF, 0, 0, 0x16 },
- Package() { 0x001CFFFF, 0, 0, 0x11 },
- Package() { 0x001CFFFF, 1, 0, 0x10 },
- Package() { 0x001CFFFF, 2, 0, 0x12 },
- Package() { 0x001CFFFF, 3, 0, 0x13 },
- Package() { 0x001DFFFF, 0, 0, 0x15 },
- Package() { 0x001DFFFF, 1, 0, 0x13 },
- Package() { 0x001DFFFF, 2, 0, 0x12 },
- Package() { 0x001DFFFF, 3, 0, 0x10 },
- Package() { 0x001EFFFF, 0, 0, 0x16 },
- Package() { 0x001EFFFF, 1, 0, 0x14 },
- Package() { 0x001FFFFF, 0, 0, 0x12 },
- Package() { 0x001FFFFF, 1, 0, 0x13 },
- Package() { 0x001FFFFF, 3, 0, 0x10 }
- })
- } Else {
- Return (Package() {
- Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }
- })
- }
-}
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index b6e61eb..136b9a6 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -41,22 +41,21 @@
device pci 00.0 on # Host bridge
subsystemid 0x8086 0x7270
end
- device pci 02.0 on # VGA controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # VGA controller
subsystemid 0x8086 0x7270
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -79,11 +78,20 @@
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
+ ioapic_irq 2 INTA 0x16
subsystemid 0x8384 0x7680
end
- device pci 1c.0 on end # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # Ethernet
device pci 1c.1 on end # Atheros WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x8086 0x7270
end
device pci 1d.1 on # USB UHCI
@@ -98,7 +106,10 @@
device pci 1d.7 on # USB2 EHCI
subsystemid 0x8086 0x7270
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x8086 0x7270
end
device pci 1f.1 on # IDE
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 92dfe74..02255e6 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -158,25 +158,6 @@
/* V1CAP Virtual Channel 1 Resource Capability */
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- RCBA32(0x3108) = 0x10004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00214321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000001;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0235;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); /* Required. */
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
index 6f6eaae..0448e9a 100644
--- a/src/mainboard/asus/p5gc-mx/Kconfig
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -33,6 +33,7 @@
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_EDID
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 4aaa33f..0000000
--- a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 19 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 },
- Package() { 0x001fffff, 3, 0, 19 },
-
- })
-
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index 824beed..a24b97c 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -31,23 +31,19 @@
end
device pci 01.0 on # i945 PCIe root port
subsystemid 0x1458 0x5000
- ioapic_irq 2 INTA 0x10
end
device pci 02.0 on # vga controller
subsystemid 0x1458 0xd000
ioapic_irq 2 INTA 0x10
end
-
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x86"
- register "pirqd_routing" = "0x85"
- register "pirqe_routing" = "0x83"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x85"
-
register "gpe0_en" = "0"
register "ide_legacy_combined" = "0x0"
@@ -58,33 +54,35 @@
register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on # High Definition Audio
- ioapic_irq 2 INTA 0x10
+ ioapic_irq 2 INTA 0x16
end
- device pci 1c.0 on end # PCIe
+ device pci 1c.0 on # PCIe
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
device pci 1c.1 on end # PCIe
#device pci 1c.2 off end # PCIe port 3
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on # USB UHCI
- ioapic_irq 2 INTA 0x10
- end
- device pci 1d.1 on # USB UHCI
- ioapic_irq 2 INTB 0x11
- end
- device pci 1d.2 on # USB UHCI
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10
end
- device pci 1d.3 on # USB UHCI
- ioapic_irq 2 INTD 0x13
- end
- device pci 1d.7 on # USB2 EHCI
- ioapic_irq 2 INTA 0x10
- end
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # LPC bridge
- ioapic_irq 2 INTA 0x10
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
chip superio/winbond/w83627dhg
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
index cdcd9cc..e734415 100644
--- a/src/mainboard/getac/p470/Kconfig
+++ b/src/mainboard/getac/p470/Kconfig
@@ -38,6 +38,7 @@
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select INTEL_EDID
select INTEL_INT15
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 415d9a3..16db39c 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -29,20 +29,21 @@
device domain 0 on
device pci 00.0 on end # host bridge
- device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
- device pci 02.1 on end # display controller
+ # autodetect:
+ #device pci 01.0 off end # i945 PCIe root port
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10
+ end # vga controller
+ #device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0a"
- register "pirqb_routing" = "0x0a"
- register "pirqc_routing" = "0x0a"
- register "pirqd_routing" = "0x0a"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x0a"
- register "pirqh_routing" = "0x0a"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -63,26 +64,43 @@
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe port 1
+ device pci 1b.0 on # High Definition Audio
+ ioapic_irq 2 INTA 0x16
+ end
+
+ device pci 1c.0 on # PCIe port 1
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
device pci 1c.1 on end # PCIe port 2
device pci 1c.2 on end # PCIe port 3
device pci 1c.3 on end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14
chip southbridge/ti/pcixx12
end
end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/fdc37n972
device pnp 2e.0 off # Floppy
end
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index d1552a6..a527629 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -149,21 +149,6 @@
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 4aaa33f..0000000
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 17 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 19 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 17 },
- Package() { 0x001fffff, 2, 0, 18 },
- Package() { 0x001fffff, 3, 0, 19 },
-
- })
-
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index acf743b..0692a41 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -33,23 +33,19 @@
end
device pci 01.0 on # i945 PCIe root port
subsystemid 0x1458 0x5000
- ioapic_irq 2 INTA 0x10
end
device pci 02.0 on # vga controller
subsystemid 0x1458 0xd000
ioapic_irq 2 INTA 0x10
end
-
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x8c"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x83"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x85"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -82,33 +78,40 @@
register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on # High Definition Audio
- ioapic_irq 2 INTA 0x10
+ ioapic_irq 2 INTA 0x16
end
- device pci 1c.0 on end # PCIe
+ device pci 1c.0 on # PCIe
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
device pci 1c.1 on end # PCIe
#device pci 1c.2 off end # PCIe port 3
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on # USB UHCI
- ioapic_irq 2 INTA 0x10
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
end
device pci 1d.1 on # USB UHCI
- ioapic_irq 2 INTB 0x11
end
device pci 1d.2 on # USB UHCI
- ioapic_irq 2 INTC 0x12
end
device pci 1d.3 on # USB UHCI
- ioapic_irq 2 INTD 0x13
end
device pci 1d.7 on # USB2 EHCI
- ioapic_irq 2 INTA 0x10
end
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # LPC bridge
- ioapic_irq 2 INTA 0x10
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10
+
chip superio/ite/it8718f # Super I/O
register "TMPIN1" = "THERMAL_RESISTOR"
register "TMPIN2" = "THERMAL_RESISTOR"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 9789d2a..b8d18a8 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -81,9 +81,6 @@
static void rcba_config(void)
{
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = 0x003c0061;
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
index ae57e5b..80c1ec3 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -34,6 +34,7 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
+ select DRIVERS_GENERIC_IOAPIC
config MMCONF_BASE_ADDRESS
hex
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
deleted file mode 100644
index 46e8a4a..0000000
--- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for x4x */
-
-/* PCI Interrupt Routing */
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- /* PEG */
- Package() { 0x0001ffff, 0, 0, 16 },
- /* Internal GFX */
- Package() { 0x0002ffff, 0, 0, 16 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, 0, 16 },
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- /* USB and EHCI 0:1d.x */
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 1, 0, 19 },
- })
- } Else {
- Return (Package() {
- /* PEG */
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* Internal GFX */
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- /* USB and EHCI 0:1d.x */
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index 60004d2..e2e947e 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -29,22 +29,22 @@
subsystemid 0x1458 0x5000
end
device pci 2.0 on # Integrated graphics controller
+ ioapic_irq 2 INTA 0x10
subsystemid 0x1458 0xd000
end
device pci 2.1 on # Integrated graphics controller 2
subsystemid 0x1458 0xd001
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
device pci 3.0 off end # ME
device pci 3.1 off end # ME
chip southbridge/intel/i82801gx # Southbridge
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
register "ide_legacy_combined" = "0x0" # Combined mode broken
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
@@ -54,8 +54,15 @@
device pci 1b.0 on # Audio
subsystemid 0x1458 0xa002
+ ioapic_irq 2 INTA 0x16
+ subsystemid 0x8384 0x7680
end
- device pci 1c.0 on end # PCIe 1
+ device pci 1c.0 on # PCIe 1
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
device pci 1c.1 on # PCIe 2 (NIC)
device pci 00.0 on # PCI 10ec:8168
subsystemid 0x1458 0xe000
@@ -65,6 +72,10 @@
device pci 1c.3 on end # PCIe 4
device pci 1d.0 on # USB
subsystemid 0x1458 0x5004
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
end
device pci 1d.1 on # USB
subsystemid 0x1458 0x5004
@@ -81,6 +92,9 @@
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge
subsystemid 0x1458 0x5001
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
chip superio/ite/it8718f # Super I/O
register "TMPIN1" = "THERMAL_RESISTOR"
register "TMPIN2" = "THERMAL_RESISTOR"
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 0a1470b..a1ec0c8 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -87,20 +87,6 @@
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
- /* IRQ routing */
- RCBA32(0x3100) = 0x00002210;
- RCBA32(0x3104) = 0x00002100;
- RCBA32(0x3108) = 0x10004321;
- RCBA32(0x310c) = 0x00214321;
- RCBA32(0x3110) = 0x00000001;
- RCBA32(0x3140) = 0x00410032;
- RCBA32(0x3144) = 0x32100237;
- RCBA32(0x3148) = 0x00000000;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
-
RCBA32(0x3410) = 0x00190464;
RCBA32(0x3418) = 0x003c0063;
RCBA32(0x341c) = 0x00000000;
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 3208a93..d98a02b 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -16,6 +16,7 @@
select BOARD_ROMSIZE_KB_512
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 0db7bc7..0000000
--- a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- //Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 17 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19},
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index c63e5d6..45a87e9 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -14,19 +14,19 @@
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10
+ end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x07"
- register "pirqc_routing" = "0x05"
- register "pirqd_routing" = "0x07"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x06"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -41,22 +41,37 @@
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- #device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16
+ end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/winbond/w83627ehg
device pnp 4e.0 off end # Floppy
device pnp 4e.1 off end # Parport
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 7088f1d..65ffbc0 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -130,21 +130,6 @@
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 7131b3a..edf5d98 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -27,6 +27,7 @@
select INTEL_INT15
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
+ select DRIVERS_GENERIC_IOAPIC
config MAX_CPUS
int
diff --git a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
deleted file mode 100644
index 3fa6fdb..0000000
--- a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for pineview */
-/* FIXME: EHCI controller not working yet */
-
-/* PCI Interrupt Routing */
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- /* Internal GFX */
- Package() { 0x0002ffff, 0, 0, 16 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, 0, 22 },
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- /* USB and EHCI 0:1d.x */
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- Package() { 0x001dffff, 0, 0, 23 },
- /* PCI 0:1e.0 */
- Package() { 0x001effff, 0, 0, 22 },
- /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 1, 0, 19 },
- })
- } Else {
- Return (Package() {
- /* Internal GFX */
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- /* USB and EHCI 0:1d.x */
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- /* PCI 0:1e.0 */
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index c5b885f..ffca4ca 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -27,35 +27,49 @@
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 off end # PEG
- device pci 2.0 on end # Integrated graphics controller
+ device pci 2.0 on # Integrated graphics controller
+ ioapic_irq 2 INTA 0x10
+ end
device pci 2.1 on end # Integrated graphics controller 2
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx # Southbridge
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio
+ ioapic_irq 2 INTA 0x16
device pci 1c.0 on # PCIe 1
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
device pci 0.0 on end # NIC
end
device pci 1c.1 on end # PCIe 2
device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4
- device pci 1d.0 on end # USB
+ device pci 1d.0 on # USB
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10
+ end
device pci 1d.1 on end # USB
device pci 1d.2 on end # USB
device pci 1d.3 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10
chip superio/winbond/w83627thg # Super I/O
device pnp 4e.0 off end # Floppy
device pnp 4e.1 on # Parallel port
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 3209d81..88cf837 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -71,27 +71,6 @@
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- RCBA32(0x3108) = 0x10004321;
-
- RCBA32(0x3104) = 0x00002100;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00214321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000001;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
RCBA32(0x3418) = 0x003000e2;
RCBA32(0x3418) |= 1;
}
@@ -128,4 +107,5 @@
ram_check(0x200000,0x300000);
rcba_config();
+ ich7_setup_interrupts();
}
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 4887dbb..e9cd386 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -31,6 +31,7 @@
select CHANNEL_XOR_RANDOMIZATION
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_EDID
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
deleted file mode 100644
index a7fcc85..0000000
--- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 22 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index e8c2792..07ba807 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -27,19 +27,18 @@
subsystemid 0x8086 0x464c inherit
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x07"
- register "pirqc_routing" = "0x05"
- register "pirqd_routing" = "0x07"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x06"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -54,22 +53,36 @@
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/lpc47m15x
device pnp 2e.0 off # Floppy
end
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e769fc5..deb4cbf 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -55,21 +55,6 @@
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index 2a3cfe2..3c60c99 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -17,6 +17,7 @@
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
select OVERRIDE_CLOCK_DISABLE
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
deleted file mode 100644
index efb94c6..0000000
--- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 17 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19},
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index c768b64..8651dc6 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -14,19 +14,19 @@
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on # vga controller
+ ioapic_irq 2 INTA 0x10
+ end
device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
+ chip southbridge/intel/i82801gx
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -40,23 +40,38 @@
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
- device pci 1c.1 on end # PCIe
- device pci 1c.2 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16
+ end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.3 on end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
- chip superio/winbond/w83627thg
+ device pci 1f.0 on # LPC bridge
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10
+ chip superio/winbond/w83627thg
device pnp 2e.0 off # Floppy
end
device pnp 2e.1 on # Parallel port
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 3b3ff66..9c8eb3c 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -185,21 +185,6 @@
/* Set up virtual channel 0 */
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x3241;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3210;
- RCBA16(0x3148) = 0x3210;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Now, this is a bit ugly. As per PCI specification, function 0 of a
* device always has to be implemented. So disabling ethernet port 1
* would essentially disable all three ethernet ports of the mainboard.
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index 289c06a..41d2136 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -25,6 +25,7 @@
select H8_DOCK_EARLY_INIT
select HAVE_CMOS_DEFAULT
select INTEL_EDID
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
deleted file mode 100644
index f0d76db..0000000
--- a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x10 } // SATA
- })
- } Else {
- Return (Package() {
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA
- })
- }
-}
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 6ad054c..9f1b0b9 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -47,23 +47,22 @@
end
end
- device pci 02.0 on # GMA Graphics controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # GMA Graphics controller
subsystemid 0x17aa 0x201a
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -83,14 +82,23 @@
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
- device pci 1b.0 on # Audio Controller
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 # Audio Controller
subsystemid 0x17aa 0x2010
end
- device pci 1c.0 on # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 # Ethernet
subsystemid 0x17aa 0x2001
end
device pci 1c.1 on end # WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.1 on # USB UHCI
@@ -105,7 +113,9 @@
device pci 1d.7 on # USB2 EHCI
subsystemid 0x17aa 0x200b
end
- device pci 1e.0 on # PCI Bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 # PCI Bridge
chip southbridge/ti/pci1x2x
device pci 00.0 on
subsystemid 0x17aa 0x2012
@@ -115,7 +125,10 @@
end
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 2686635..5287258 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -82,25 +82,6 @@
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00001230;
- RCBA32(0x3108) = 0x40004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00004321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000002;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 7667a75..77f094a 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -28,6 +28,7 @@
select H8_DOCK_EARLY_INIT
select DRIVERS_LENOVO_WACOM
select INTEL_EDID
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
deleted file mode 100644
index f0d76db..0000000
--- a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x10 } // SATA
- })
- } Else {
- Return (Package() {
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA
- })
- }
-}
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 28b63d3..cb626f0 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -41,22 +41,21 @@
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2017
end
- device pci 02.0 on # VGA controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # VGA controller
subsystemid 0x17aa 0x201a
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -78,11 +77,20 @@
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
+ ioapic_irq 2 INTA 0x16
subsystemid 0x17aa 0x2010
end
- device pci 1c.0 on end # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # Ethernet
device pci 1c.1 on end # Atheros WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.1 on # USB UHCI
@@ -97,7 +105,10 @@
device pci 1d.7 on # USB2 EHCI
subsystemid 0x17aa 0x200b
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 51624a0..43d9ba1 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -82,25 +82,6 @@
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00001230;
- RCBA32(0x3108) = 0x40004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00004321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000002;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index efe75a3..b1f2da8 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -19,6 +19,7 @@
select BOARD_ROMSIZE_KB_1024
select CHANNEL_XOR_RANDOMIZATION
select INTEL_INT15
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
deleted file mode 100644
index a7d999e..0000000
--- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 22 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 1, 0, 20 },
- Package() { 0x001fffff, 3, 0, 16 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
- })
- }
-}
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 28f8f43..748f6fd 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -32,19 +32,18 @@
device pci 00.0 on end # host bridge
# auto detection:
#device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -63,19 +62,30 @@
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14
chip southbridge/ti/pci7420
register "smartcard_enabled" = "0x0"
device pci 3.0 on end
@@ -86,7 +96,10 @@
end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/lpc47n227
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index a488488..98e3edd 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -120,21 +120,6 @@
{
/* Set up virtual channel 0 */
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index 5877b0e..7b3917d 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -228,6 +228,3 @@
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/i945_pci_irqs.asl"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 0a2c99e..97d7edd 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -929,6 +929,8 @@
void i945_late_initialization(int s3resume)
{
+ ich7_setup_interrupts();
+
i945_setup_egress_port();
ich7_setup_root_complex_topology();
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 330ace1..9fd7230 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -356,6 +356,7 @@
/* provided by mainboard code */
void setup_ich7_gpios(void);
+void southbridge_setup_interrupts(void);
/* debugging functions */
void print_pci_devices(void);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index e1cf95f..41688aa 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -165,15 +165,6 @@
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
- RCBA32(0x3100) = 0x42210;
- RCBA32(0x3108) = 0x10004321;
- RCBA32(0x310c) = 0x00214321;
- RCBA32(0x3110) = 0x1;
- RCBA32(0x3140) = 0x01460132;
- RCBA32(0x3142) = 0x02370146;
- RCBA32(0x3144) = 0x32010237;
- RCBA32(0x3146) = 0x01463201;
- RCBA32(0x3148) = 0x146;
}
static void pineview_setup_bars(void)
diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl
index 530fdfa..90f15c7 100644
--- a/src/northbridge/intel/x4x/acpi/hostbridge.asl
+++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl
@@ -229,6 +229,3 @@
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/x4x_pci_irqs.asl"
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index a556adc..2ba0f3f 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -241,6 +241,7 @@
void x4x_late_init(int s3resume)
{
+ ich7_setup_interrupts();
init_egress();
init_dmi();
x4x_prepare_resume(s3resume);
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 8a9aff4..70d2b50 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -185,3 +185,5 @@
// SMBus
#include "smbus.asl"
+
+#include "irq.asl"
diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/southbridge/intel/i82801gx/acpi/irq.asl
similarity index 96%
rename from src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
rename to src/southbridge/intel/i82801gx/acpi/irq.asl
index 5bbf144..3d8c72d 100644
--- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/irq.asl
@@ -14,11 +14,6 @@
* GNU General Public License for more details.
*/
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
// PCI Interrupt Routing
Method(_PRT)
{
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index e89fcc4..8394592 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -17,18 +17,6 @@
#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
struct southbridge_intel_i82801gx_config {
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
/**
* GPI Routing configuration
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 11da3ec..1983e77 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -52,3 +52,24 @@
return 0;
}
+
+void ich7_setup_interrupts(void)
+{
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042220;
+ RCBA32(0x3108) = 0x10004321;
+ /* Device 1d interrupt pin register */
+ RCBA32(0x310c) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(0x3110) = 0x00000001;
+
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0232;
+ RCBA16(0x3142) = 0x3246;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3201;
+ RCBA16(0x3148) = 0x3216;
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 85cf6db..97816fe 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -51,6 +51,7 @@
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
int southbridge_detect_s3_resume(void);
+void ich7_setup_interrupts(void);
#endif
#endif
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index e650d82..ff11a33 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -91,46 +91,38 @@
static void i82801gx_pirq_init(device_t dev)
{
device_t irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
-
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
-
- /* Eric Biederman once said we should let the OS do this.
- * I am not so sure anymore he was right.
+ /* Interrupt 11 is not used by legacy devices and so can always be used
+ * for PCI interrupts. Full legacy IRQ routing is complicated and hard
+ * to get right. Fortunately all modern OS use MSI and so it's not that
+ * big of an issue anyway. Still we have to provide a reasonable
+ * default. Using interrupt 11 for it everywhere is a working default.
+ * ACPI-aware OS can move it to any interrupt and others will just leave
+ * them at default.
*/
+ const u8 pirq_routing = 11;
+
+ pci_write_config8(dev, PIRQA_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQB_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQC_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQD_ROUT, pirq_routing);
+
+ pci_write_config8(dev, PIRQE_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQF_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
+ u8 int_pin = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1:
- /* INTA# */ int_line = config->pirqa_routing; break;
- case 2:
- /* INTB# */ int_line = config->pirqb_routing; break;
- case 3:
- /* INTC# */ int_line = config->pirqc_routing; break;
- case 4:
- /* INTD# */ int_line = config->pirqd_routing; break;
- }
-
- if (!int_line)
+ if (int_pin == 0)
continue;
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
}
}
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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