[coreboot-gerrit] Change in coreboot[master]: vendorcode/amd/pi/00670F00: Clarify CAR disable

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/18492 )

Change subject: vendorcode/amd/pi/00670F00: Clarify CAR disable
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Patch Set 5:

(1 comment)

> AGESATM--Arch2008 44065 Rev. 3.04 January 2017

I didn’t realize they finally released a new spec.  I would argue that the spec has been incorrect regarding the precise functionality of the “Entry Point Procedures” for a while.  I’ve inspected their effects on the system with HDT and I’m confident things are working as we expect.  The revision history for the 3.04 release doesn’t change my mind.

https://review.coreboot.org/#/c/18492/5/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
File src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc:

Line 1298: * AMD_DISABLE_STACK:  Copy CAR data to DRAM and destroy the stack inside the
> 'flush cachelines' or 'invalidate with write-back'
> 'flush cachelines' or 'invalidate with write-back'

Does that wording move this patch forward?

> Can you give me your impression of the actual address ranges that are flushed here? I will then give you mine.

It’s anything dirty (i.e. Modified to use proper terminology) and is subject to the “Determining The Access Destination…” list, including MTRR rules.  While this could potentially be any addressable non-MMIO and non-BIOS region that were inadverently touched, it seems it should be the stacks and coreboot global stuff from 30000-50000, as well as the non-cbmem heap at 10000000.  Also, once we have early cbmem, the heap will get allocated from there instead.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328
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