[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18381 )

Change subject: soc/intel/common/block: Add cache as ram init and teardown code
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Patch Set 35:

(1 comment)

https://review.coreboot.org/#/c/18381/35/src/soc/intel/common/block/cpu/car/cache_as_ram.S
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

PS35, Line 107: 	/* Configure CAR region as write-back (WB) */
              : 	mov	$MTRR_PHYS_BASE(0), %ecx
              : 	mov	$CONFIG_DCACHE_RAM_BASE, %eax
              : 	or	$MTRR_TYPE_WRBACK, %eax
              : 	xor	%edx,%edx
              : 	wrmsr
> Move this into each of the #if and #elif clauses.
Done


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Gerrit-MessageType: comment
Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Gerrit-PatchSet: 35
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
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Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
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