[coreboot-gerrit] Change in coreboot[master]: google/fizz: Transfer gpio from schematic
Martin Roth (Code Review)
gerrit at coreboot.org
Thu Mar 23 21:09:43 CET 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18797 )
Change subject: google/fizz: Transfer gpio from schematic
......................................................................
google/fizz: Transfer gpio from schematic
Transfer the gpio assignments in the fizz schematic
into gpio.h.
BUG=b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
Change-Id: If05aa2859f2511c3f616dc3fb38bca4fb8524697
Signed-off-by: Shelley Chen <shchen at chromium.org>
Reviewed-on: https://review.coreboot.org/18797
Reviewed-by: Furquan Shaikh <furquan at google.com>
Tested-by: build bot (Jenkins)
---
M src/mainboard/google/fizz/gpio.h
1 file changed, 144 insertions(+), 144 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 428b283..24819d8 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -25,12 +25,6 @@
/* BIOS Flash Write Protect */
#define GPIO_PCH_WP GPP_C23
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0 GPP_C12
-#define GPIO_MEM_CONFIG_1 GPP_C13
-#define GPIO_MEM_CONFIG_2 GPP_C14
-#define GPIO_MEM_CONFIG_3 GPP_C15
-
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
@@ -41,166 +35,173 @@
/* Pad configuration in ramstage */
/* Leave eSPI pins untouched from default settings */
static const struct pad_config gpio_table[] = {
-/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */
+/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */
/* ESPI_IO0 */
/* ESPI_IO1 */
/* ESPI_IO2 */
/* ESPI_IO3 */
/* ESPI_CS# */
-/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
-/* PIRQA# */ PAD_CFG_NC(GPP_A7),
-/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
+/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
+/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CDZ */
+/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
/* ESPI_CLK */
-/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
-/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */
+/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
-/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
+/* SUSWARN# */ PAD_CFG_GPI(GPP_A13, NONE, DEEP), /* eSPI mode */
/* ESPI_RESET# */
-/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
-/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
-/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE,
- PLTRST), /* ACCEL_GYRO_INT_L */
+/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
+/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* HDPO */
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
-/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */
-/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */
-/* VRALERT# */ PAD_CFG_NC(GPP_B2),
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */
/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
-/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5),
-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */
-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */
-/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
-/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
-/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
-/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
-/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* SPKR */ PAD_CFG_NC(GPP_B14),
-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
-/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */
-/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */
-/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */
-/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */
-/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,
+ NF1), /* CLK_PCIE_LAN_REQ# */
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_SSD# */
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_NGFF1# */
+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */
+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */
+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_WLAN# */
+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* PCH_SPI_H1_3V3_CS_L */
+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), /* PCH_SPI_H1_3V3_CLK */
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), /* PCH_SPI_H1_3V3_MISO */
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), /* PCH_SPI_H1_3V3_MOSI */
+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */
+/* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */
+/* GSPI1_MISO */ PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */
+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
+/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */
-/* SMBCLK */ PAD_CFG_NC(GPP_C0),
-/* SMBDATA */ PAD_CFG_NC(GPP_C1),
-/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
+/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
/* SML0CLK */ PAD_CFG_NC(GPP_C3),
/* SML0DATA */ PAD_CFG_NC(GPP_C4),
-/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
+/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */ PAD_CFG_NC(GPP_C7),
-/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */
-/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
-/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
-/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
-/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
-/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
-/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */
-/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */
+/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */
+/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, 20K_PU, DEEP), /* GPIO1 */
+/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, 20K_PU, DEEP), /* GPIO2 */
+/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, 20K_PU, DEEP), /* GPIO3 */
+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, 20K_PU, DEEP), /* GPIO4 */
+/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* SKU_ID0 */
+/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* SKU_ID1 */
+/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* SKU_ID2 */
+/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
-/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1,
- DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */
+/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, NONE,
+ DEEP), /* SCREW_SPI_WP_STATUS */
-/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
-/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */
-/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */
-/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */
-/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
-/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP,
- NF1), /* ISH_SENSOR */
-/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP,
- NF1), /* ISH_SENSOR */
+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */
+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */
+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE,
PLTRST), /* HP_IRQ_GPIO */
-/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
-/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE,
- PLTRST), /* SPKR_INT_L */
+/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10),
+/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
-/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
-/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */
-/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */
-/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */
-/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */
-/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
-/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */
-/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */
+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
+/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */
+/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */
+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */
+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
- PLTRST), /* TPM_INT_L */
-/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
-/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
+ PLTRST), /* H1_PCH_INT_ODL */
+/* SATAXPCIE1 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* MB_PCIE_SATA#_DET */
+/* SATAXPCIE2 */ PAD_CFG_GPI(GPP_E2, 20K_PU,
+ DEEP), /* DB_PCIE_SATA#_DET */
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
-/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */
-/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */
-/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */
-/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE,
- PLTRST), /* TOUCHSCREEN_INT_L */
-/* SATALED# */ PAD_CFG_NC(GPP_E8),
-/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
+/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */
+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */
+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
+/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */
+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,
- NF1), /* USB_C1_OC_ODL */
-/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */
-/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */
-/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
- NF1), /* USB_C0_DP_HPD */
+ NF1), /* Rear Dual-Stack USB Ports */
+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
+ NF1), /* Front USB Ports */
+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,
+ NF1), /* Rear Single USB Port */
+/* DDPB_HPD0 */ PAD_CFG_GPI_APIC(GPP_E13, NONE,
+ PLTRST), /* INT_HDMI_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
- NF1), /* USB_C1_DP_HPD */
-/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */
-/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
+ NF1), /* DDI2_HPD */
+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */
+/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
-/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
-/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
-/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,
+ NF1), /* HDMI_DDCCLK_SW */
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,
+ NF1), /* HDMI_DDCCLK_DATA */
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
-/* The next 4 pads are for bit banging the amplifiers, default to I2S */
-/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
-/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */
-/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */
-/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */
-/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */
-/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */
-/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/
-/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */
-/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */
-/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
-/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
-/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
-/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
-/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
-/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
-/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */
+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */
+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */
+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */
+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SDA */
+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SCL */
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),
+/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),
+/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
+ NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
+/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
+ NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
/* RSVD */ PAD_CFG_NC(GPP_F23),
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
@@ -208,33 +209,32 @@
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
-/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
-/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */
-/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
-/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
-/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */
+/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */
+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
+/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */
/* RSVD */ PAD_CFG_NC(GPD7),
-/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */
-/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
+/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */
+/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */
/* LANPHYC */ PAD_CFG_NC(GPD11),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
-/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SDA */
+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SCL */
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
- PLTRST), /* TPM_INT_L */
+ PLTRST), /* H1_PCH_INT_ODL */
/* Ensure UART pins are in native mode for H1. */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: If05aa2859f2511c3f616dc3fb38bca4fb8524697
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
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