[coreboot-gerrit] Change in coreboot[master]: google/fizz: Remove poppy-specific configs
Martin Roth (Code Review)
gerrit at coreboot.org
Thu Mar 23 20:46:06 CET 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18857 )
Change subject: google/fizz: Remove poppy-specific configs
......................................................................
google/fizz: Remove poppy-specific configs
- Remove spd files/directory
- Remove audio blobs
- Remove dptf.asl contents
- Remove MKBP
- Remove acpi table initialization
BUG=b:35775024
BRANCH=None
TEST=Compiles successfully
Change-Id: I5d717d23224956ee1653c5ded28abd05cd254c3a
Signed-off-by: Shelley Chen <shchen at chromium.org>
Reviewed-on: https://review.coreboot.org/18857
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/Makefile.inc
M src/mainboard/google/fizz/acpi/dptf.asl
M src/mainboard/google/fizz/ec.h
M src/mainboard/google/fizz/mainboard.c
M src/mainboard/google/fizz/romstage.c
M src/mainboard/google/fizz/smihandler.c
D src/mainboard/google/fizz/spd/Makefile.inc
D src/mainboard/google/fizz/spd/empty.spd.hex
D src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
D src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
D src/mainboard/google/fizz/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
D src/mainboard/google/fizz/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
D src/mainboard/google/fizz/spd/spd.c
D src/mainboard/google/fizz/spd/spd.h
15 files changed, 6 insertions(+), 449 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index e90e05a..a3be595 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -5,20 +5,17 @@
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
- select DRIVERS_I2C_HID
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
- select DRIVERS_I2C_MAX98927
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
config CHROMEOS
select EC_GOOGLE_CHROMEEC_SWITCHES
- select LID_SWITCH
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
config GBB_HWID
@@ -41,11 +38,4 @@
config MAX_CPUS
int
default 8
-
-config INCLUDE_NHLT_BLOBS
- bool "Include blobs for audio."
- select NHLT_DMIC_2CH
- select NHLT_DMIC_4CH
- select NHLT_MAX98927
- select NHLT_RT5663
endif
diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc
index d5d8b51..d74b707 100644
--- a/src/mainboard/google/fizz/Makefile.inc
+++ b/src/mainboard/google/fizz/Makefile.inc
@@ -13,8 +13,6 @@
## GNU General Public License for more details.
##
-subdirs-y += spd
-
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl
index f8e5f5c..e69de29 100644
--- a/src/mainboard/google/fizz/acpi/dptf.asl
+++ b/src/mainboard/google/fizz/acpi/dptf.asl
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define DPTF_CPU_PASSIVE 94
-#define DPTF_CPU_CRITICAL 99
-
-#define DPTF_TSR0_SENSOR_ID 1
-#define DPTF_TSR0_SENSOR_NAME "Ambient"
-#define DPTF_TSR0_PASSIVE 55
-#define DPTF_TSR0_CRITICAL 70
-
-#define DPTF_TSR1_SENSOR_ID 2
-#define DPTF_TSR1_SENSOR_NAME "Charger"
-#define DPTF_TSR1_PASSIVE 55
-#define DPTF_TSR1_CRITICAL 75
-
-#define DPTF_TSR2_SENSOR_ID 3
-#define DPTF_TSR2_SENSOR_NAME "DRAM"
-#define DPTF_TSR2_PASSIVE 52
-#define DPTF_TSR2_CRITICAL 75
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
- Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
- Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
- Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
-})
-
-Name (DTRT, Package () {
- /* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
- /* Charger Effect on Temp Sensor 1 */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
- /* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
- 0x2, /* Revision */
- Package () { /* Power Limit 1 */
- 0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 1600, /* PowerLimitMinimum */
- 4500, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 200 /* StepSize */
- },
- Package () { /* Power Limit 2 */
- 1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 3000, /* PowerLimitMinimum */
- 7000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 1000 /* StepSize */
- }
-})
-
-/* Include DPTF */
-#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/fizz/ec.h b/src/mainboard/google/fizz/ec.h
index d734d12..5a91713 100644
--- a/src/mainboard/google/fizz/ec.h
+++ b/src/mainboard/google/fizz/ec.h
@@ -22,9 +22,7 @@
#include "gpio.h"
#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
@@ -33,16 +31,11 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/*
* EC can wake from S3 with lid or power button or key press or
@@ -50,8 +43,7 @@
*/
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
@@ -66,13 +58,10 @@
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
+/* Provide wake pin for EC */
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
-
-#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */
#endif
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 0cd0643..d515d29 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -17,61 +17,17 @@
#include <console/console.h>
#include <device/device.h>
#include <ec/ec.h>
-#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
-
-static const char *oem_id_maxim = "GOOGLE";
-static const char *oem_table_id_maxim = "FIZZMAX";
static void mainboard_init(device_t dev)
{
mainboard_ec_init();
}
-static unsigned long mainboard_write_acpi_tables(device_t device,
- unsigned long current, acpi_rsdp_t *rsdp)
-{
- uintptr_t start_addr;
- uintptr_t end_addr;
- struct nhlt *nhlt;
-
- start_addr = current;
-
- nhlt = nhlt_init();
-
- if (nhlt == NULL)
- return start_addr;
-
- /* 2 Channel DMIC array. */
- if (nhlt_soc_add_dmic_array(nhlt, 2))
- printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
-
- /* 4 Channel DMIC array. */
- if (nhlt_soc_add_dmic_array(nhlt, 4))
- printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
-
- /* Maxim MAX98927 Smart Amps for left and right channel */
- if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0))
- printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n");
-
- /* Realtek RT5663 Headset codec. */
- if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1))
- printk(BIOS_ERR, "Couldn't add Realtek RT5663.\n");
-
- end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
- oem_id_maxim, oem_table_id_maxim, 0);
-
- if (end_addr != start_addr)
- acpi_add_table(rsdp, (void *)start_addr);
-
- return end_addr;
-}
-
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 34aaad0..8bcfcd3 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -18,34 +18,14 @@
#include <fsp/soc_binding.h>
-#include "spd/spd.h"
-
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
- /* DQ byte map */
- const u8 dq_map[2][12] = {
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
- 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
- { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33,
- 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 }
- };
- /* DQS CPU<>DRAM map */
- const u8 dqs_map[2][8] = {
- { 2, 3, 1, 0, 4, 7, 6, 5 },
- { 5, 6, 0, 3, 4, 7, 2, 1 },
- };
/* Rcomp resistor */
const u16 rcomp_resistor[] = { 200, 81, 162 };
/* Rcomp target */
const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
- memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map));
- memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map));
memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
-
- mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
- mem_cfg->MemorySpdDataLen = SPD_LEN;
}
diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c
index d7ef509..5f05b2e 100644
--- a/src/mainboard/google/fizz/smihandler.c
+++ b/src/mainboard/google/fizz/smihandler.c
@@ -32,7 +32,6 @@
int mainboard_smi_apmc(u8 apmc)
{
- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
- MAINBOARD_EC_SMI_EVENTS);
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, 0);
return 0;
}
diff --git a/src/mainboard/google/fizz/spd/Makefile.inc b/src/mainboard/google/fizz/spd/Makefile.inc
deleted file mode 100644
index 71833bb..0000000
--- a/src/mainboard/google/fizz/spd/Makefile.inc
+++ /dev/null
@@ -1,41 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2017 Google Inc.
-## Copyright (C) 2016 Intel Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-SPD_SOURCES = empty # 0b0000
-SPD_SOURCES += empty # 0b0001
-SPD_SOURCES += empty # 0b0010
-SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0011
-SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0100
-SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0101
-SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0110
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/fizz/spd/empty.spd.hex b/src/mainboard/google/fizz/spd/empty.spd.hex
deleted file mode 100644
index 9ec39f1..0000000
--- a/src/mainboard/google/fizz/spd/empty.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex b/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
deleted file mode 100644
index bc1a2fa..0000000
--- a/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
-48 39 43 43 4E 4E 4E 43 50 54 41 4C 42 52 2D 4E
-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex b/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
deleted file mode 100644
index b9f5a1e..0000000
--- a/src/mainboard/google/fizz/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
-48 39 43 43 4E 4E 4E 46 41 47 4D 4C 4C 52 2D 4E
-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/fizz/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex b/src/mainboard/google/fizz/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
deleted file mode 100644
index 5142334..0000000
--- a/src/mainboard/google/fizz/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 C1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 2C 00 00 00 00 00 00 00 C1 55
-4D 54 35 32 4C 31 47 36 34 44 38 51 43 2D 31 30
-37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/fizz/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex b/src/mainboard/google/fizz/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
deleted file mode 100644
index d2a0338..0000000
--- a/src/mainboard/google/fizz/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 2C 00 00 00 00 00 00 00 36 0E
-4D 54 35 32 4C 35 31 32 4D 36 34 44 34 50 51 2D
-31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/fizz/spd/spd.c b/src/mainboard/google/fizz/spd/spd.c
deleted file mode 100644
index 2fcf5a5..0000000
--- a/src/mainboard/google/fizz/spd/spd.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/byteorder.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <string.h>
-
-#include "../gpio.h"
-#include "spd.h"
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO,
- "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
- banks, ranks, rows, cols, capmb);
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-uintptr_t mainboard_get_spd_data(void)
-{
- char *spd_file;
- size_t spd_file_len;
- int spd_index;
-
- gpio_t spd_gpios[] = {
- GPIO_MEM_CONFIG_0,
- GPIO_MEM_CONFIG_1,
- GPIO_MEM_CONFIG_2,
- GPIO_MEM_CONFIG_3,
- };
-
- spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
- printk(BIOS_INFO, "SPD index %d\n", spd_index);
-
- /* Load SPD data from CBFS */
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- /* make sure we have at least one SPD in the file. */
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- /* Make sure we did not overrun the buffer */
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
- spd_index = 1;
- }
-
- spd_index *= SPD_LEN;
- mainboard_print_spd_info((uint8_t *)(spd_file + spd_index));
-
- return (uintptr_t)(spd_file + spd_index);
-}
diff --git a/src/mainboard/google/fizz/spd/spd.h b/src/mainboard/google/fizz/spd/spd.h
deleted file mode 100644
index d8a84ab..0000000
--- a/src/mainboard/google/fizz/spd/spd.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-#define SPD_MANU_OFF 148
-
-uintptr_t mainboard_get_spd_data(void);
-
-#endif
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I5d717d23224956ee1653c5ded28abd05cd254c3a
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
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Gerrit-Reviewer: build bot (Jenkins)
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