[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/18952 )

Change subject: soc/intel/common/block: Add Intel common UART code
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Patch Set 1:

> (5 comments)
 > 
 > What is the CL supposed to cover SoC-wise. I feel like intel is
 > just assuming big core is the standard when that's not true. Has
 > there been diligence done in comparing all the SoCs?

Yes.we analysed the code for UART Init in Bootblock phase for Skylake, Apollolake and GLK.The common code chunk across these SOCs is ported to common block.The GPIO programming and PCR register programming for UART Init in bootblock phase which is specific to SOC would be under SOC code.

Call from bootblock for uart Init then would configure common registers as per common code and SOC specific configuration as per SOC code.

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Gerrit-MessageType: comment
Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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