[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/18952 )

Change subject: soc/intel/common/block: Add Intel common UART code
......................................................................

soc/intel/common/block: Add Intel common UART code

Create Intel Common UART driver code.This code does
below UART configuration for bootblock phase.

* Program BAR
* Configure reset register
* Configure clock register

Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
A src/soc/intel/common/block/include/intelblocks/uart.h
A src/soc/intel/common/block/uart/Kconfig
A src/soc/intel/common/block/uart/Makefile.inc
A src/soc/intel/common/block/uart/uart.c
4 files changed, 86 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/18952/1

diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
new file mode 100644
index 0000000..2aa212c
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_UART_H
+#define SOC_INTEL_COMMON_BLOCK_UART_H
+
+
+#define SIO_REG_PPR_CLOCK	0x200
+#define SIO_REG_PPR_CLOCK_EN	(1 << 0)
+#define SIO_REG_PPR_CLOCK_UPDATE	(1 << 31)
+
+#define SIO_REG_PPR_RESETS	0x204
+#define SIO_REG_PPR_RESETS_FUNC	(1 << 0)
+#define SIO_REG_PPR_RESETS_APB	(1 << 1)
+
+void soc_uart_init(uintptr_t baseaddr);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_UART_H */
diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig
new file mode 100644
index 0000000..aecfae1
--- /dev/null
+++ b/src/soc/intel/common/block/uart/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_UART
+	bool
+	help
+	  Intel Processor common UART support
diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc
new file mode 100644
index 0000000..010e9d2
--- /dev/null
+++ b/src/soc/intel/common/block/uart/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
+
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
new file mode 100644
index 0000000..6b339af
--- /dev/null
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <intelblocks/uart.h>
+#include <soc/pci_devs.h>
+#include <soc/serialio.h>
+
+void soc_uart_init(uintptr_t baseaddr)
+{
+	device_t dev = PCH_DEVFN_UART2;
+	uint32_t tmp;
+	uint8_t *base = (void *)baseaddr;
+
+	/* Set configured UART2 base address */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, (uint32_t)base);
+
+	/* Enable memory access and bus master */
+	tmp = pci_read_config32(dev, PCI_COMMAND);
+	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+	pci_write_config32(dev, PCI_COMMAND, tmp);
+
+	/* Take UART2 out of reset */
+	tmp = read32(base + SIO_REG_PPR_RESETS);
+	tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB;
+	write32(base + SIO_REG_PPR_RESETS, tmp);
+
+	/*
+	 * Set M and N divisor inputs and enable clock.
+	 */
+	tmp = read32(base + SIO_REG_PPR_CLOCK);
+	tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
+		(SIO_REG_PPR_CLOCK_N_DIV << 16) |
+		(SIO_REG_PPR_CLOCK_M_DIV << 1);
+	write32(base + SIO_REG_PPR_CLOCK, tmp);
+
+}

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>