[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use C entry code for MTRR programming

[Barnali Sarkar (Code Review)]

Hello Aaron Durbin, dhaval v sharma, Subrata Banik, Balaji Manigandan, Paul Menzel, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/18923

to look at the new patch set (#7).

Change subject: soc/intel/skylake: Use C entry code for MTRR programming
......................................................................

soc/intel/skylake: Use C entry code for MTRR programming

Make skylake cache as ram SPI mapped MTRR programming
align with apollolake code.

Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/bootblock/cache_as_ram.S
M src/soc/intel/skylake/bootblock/cpu.c
2 files changed, 30 insertions(+), 41 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/18923/7
-- 
To view, visit https://review.coreboot.org/18923
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>