[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add configs for enabling DCI and TraceHub
Martin Roth (Code Review)
gerrit at coreboot.org
Wed Mar 22 17:42:21 CET 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18791 )
Change subject: soc/intel/skylake: Add configs for enabling DCI and TraceHub
......................................................................
soc/intel/skylake: Add configs for enabling DCI and TraceHub
Add configs for enabling Intel TraceHub and DCI for aid in debugging.
Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
Reviewed-on: https://review.coreboot.org/18791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/romstage/romstage_fsp20.c
2 files changed, 19 insertions(+), 8 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4aa7ec9..445dcb6 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -157,6 +157,11 @@
/* Trace Hub function */
u8 EnableTraceHub;
+ u32 TraceHubMemReg0Size;
+ u32 TraceHubMemReg1Size;
+
+ /* DCI Enable/Disable */
+ u8 PchDciEn;
/* Pcie Root Ports */
u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index be71e58..fbc5fe1 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -185,16 +185,12 @@
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+ const struct soc_intel_skylake_config *config)
{
- const struct device *dev;
- const struct soc_intel_skylake_config *config;
int i;
uint32_t mask = 0;
- /* Set the parameters for MemoryInit */
- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
- config = dev->chip_info;
/*
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not
* have access to the bios_reserved range so it always assumes 8MB is
@@ -207,7 +203,6 @@
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->ProbelessTrace = config->ProbelessTrace;
- m_cfg->EnableTraceHub = config->EnableTraceHub;
if (vboot_recovery_mode_enabled())
m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */
else
@@ -228,10 +223,15 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
+ const struct device *dev;
+ const struct soc_intel_skylake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
- soc_memory_init_params(m_cfg);
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ config = dev->chip_info;
+
+ soc_memory_init_params(m_cfg, config);
/* Enable DMI Virtual Channel for ME */
m_t_cfg->DmiVcm = 0x01;
@@ -240,6 +240,12 @@
m_t_cfg->SendDidMsg = 0x01;
m_t_cfg->DidInitStat = 0x01;
+ /* DCI and TraceHub configs */
+ m_t_cfg->PchDciEn = config->PchDciEn;
+ m_cfg->EnableTraceHub = config->EnableTraceHub;
+ m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
+ m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
+
mainboard_memory_init_params(mupd);
}
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamirbohra at gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
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