[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Create API to get cache size

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18922 )

Change subject: soc/intel/skylake: Create API to get cache size
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Patch Set 5:

> In short, it seems like you are complicating things and duplicating
 > APIs that are going to have to be reworked into common code anyway.
 > It seems unnecessary w.r.t. enabling the bios region as cacheable
 > in C.
 > 
 > For example, the BIOS region offset-size should be easily retrieved
 > from the fast SPI common code as a function. 

Then for now, let me abandon first 2 patch and just use CONFIG_ROM_SIZE to get rom_size for SKL. And with SPI common code patch create a API to get_bios_rom_region_size using SPI function that will be "only" used from APL mmap_boot.c and we will not use mmap_boot concept in case of big core or common code. is that okay with you?

> The register and its fields shouldn't really be exposed to something like mmap_boot.c.

Yes agree. I guess Barnali going to address that part in her SPI common code patch for sure

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Gerrit-MessageType: comment
Gerrit-Change-Id: I024e0a9e4ee33794a7ea91bc57c5ee6673825e47
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati at intel.corp-partner.google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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