[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18381 )

Change subject: soc/intel/common/block: Add cache as ram init and teardown code
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Patch Set 30:

(4 comments)

https://review.coreboot.org/#/c/18381/30//COMMIT_MSG
Commit Message:

Line 12: by reading MSR.
> booted on what devices and what combination of options? Since this is a key
Use KBL devices (KCRD and EVE) to boot with CAR_NEM_ENHANCED 
Use APL device (Reef) to boot with CAR_CQOS
Use GLK device (GLKRVP) to boot with CAR_NEM


https://review.coreboot.org/#/c/18381/29/src/soc/intel/common/block/cpu/car/cache_as_ram.S
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

Line 430
> My comment was only about fixing #1. You can enable the rom caching in c co
i think CL:18921-18923 will address this concern.


https://review.coreboot.org/#/c/18381/30/src/soc/intel/skylake/Kconfig
File src/soc/intel/skylake/Kconfig:

Line 52: 	select SOC_INTEL_COMMON_BLOCK_CAR
> You shouldn't be auto selecting this here since you are trying to make it c
Done


Line 191: 	depends on !FSP_CAR
> You don't really need a depends on here as there's no other way to select i
Done


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Gerrit-MessageType: comment
Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Gerrit-PatchSet: 30
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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