[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable XHCI clock gate control in ACPI

[Naresh Solanki (Code Review)]

Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/18879 )

Change subject: soc/intel/skylake: Enable XHCI clock gate control in ACPI
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Patch Set 2:

Also pd should be in the state:
Port C1 CC2, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1688

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Gerrit-MessageType: comment
Gerrit-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-HasComments: No