[coreboot-gerrit] Change in coreboot[master]: Remove FSP 1.0 support
Adurb Akhbar (Code Review)
gerrit at coreboot.org
Tue Mar 21 05:39:58 CET 2017
Hello Kyösti Mälkki, Werner Zeh, Aaron Durbin, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18891
to look at the new patch set (#2).
Change subject: Remove FSP 1.0 support
......................................................................
Remove FSP 1.0 support
Native code has existed for a few years now. The lack of conversion
to the native path of these platforms indicates sufficient lack of
interest to justify dropping support.
Change-Id: Ia032f950f8dc9b92f5e96368e57f513ba5598aa2
Signed-off-by: Adurb Akhbar <aakhbar at mail.com>
---
M src/Kconfig
M src/cpu/intel/Kconfig
M src/cpu/intel/Makefile.inc
D src/cpu/intel/fsp_model_206ax/Kconfig
D src/cpu/intel/fsp_model_206ax/Makefile.inc
D src/cpu/intel/fsp_model_206ax/acpi.c
D src/cpu/intel/fsp_model_206ax/acpi/cpu.asl
D src/cpu/intel/fsp_model_206ax/bootblock.c
D src/cpu/intel/fsp_model_206ax/chip.h
D src/cpu/intel/fsp_model_206ax/finalize.c
D src/cpu/intel/fsp_model_206ax/model_206ax.h
D src/cpu/intel/fsp_model_206ax/model_206ax_init.c
D src/cpu/intel/fsp_model_406dx/Kconfig
D src/cpu/intel/fsp_model_406dx/Makefile.inc
D src/cpu/intel/fsp_model_406dx/acpi.c
D src/cpu/intel/fsp_model_406dx/acpi/cpu.asl
D src/cpu/intel/fsp_model_406dx/bootblock.c
D src/cpu/intel/fsp_model_406dx/chip.h
D src/cpu/intel/fsp_model_406dx/model_406dx.h
D src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/x86/Kconfig
D src/drivers/intel/fsp1_0/Kconfig
D src/drivers/intel/fsp1_0/Makefile.inc
D src/drivers/intel/fsp1_0/cache_as_ram.inc
D src/drivers/intel/fsp1_0/fastboot_cache.c
D src/drivers/intel/fsp1_0/fsp_util.c
D src/drivers/intel/fsp1_0/fsp_util.h
D src/drivers/intel/fsp1_0/fsp_values.h
D src/drivers/intel/fsp1_0/hob.c
M src/include/reg_script.h
M src/lib/reg_script.c
D src/mainboard/adi/Kconfig
D src/mainboard/adi/Kconfig.name
D src/mainboard/adi/rcc-dff/Kconfig
D src/mainboard/adi/rcc-dff/Kconfig.name
D src/mainboard/adi/rcc-dff/Makefile.inc
D src/mainboard/adi/rcc-dff/acpi/ec.asl
D src/mainboard/adi/rcc-dff/acpi/mainboard.asl
D src/mainboard/adi/rcc-dff/acpi/platform.asl
D src/mainboard/adi/rcc-dff/acpi/superio.asl
D src/mainboard/adi/rcc-dff/acpi/thermal.asl
D src/mainboard/adi/rcc-dff/acpi_tables.c
D src/mainboard/adi/rcc-dff/board_info.txt
D src/mainboard/adi/rcc-dff/cmos.layout
D src/mainboard/adi/rcc-dff/config_seabios
D src/mainboard/adi/rcc-dff/devicetree.cb
D src/mainboard/adi/rcc-dff/dsdt.asl
D src/mainboard/adi/rcc-dff/fadt.c
D src/mainboard/adi/rcc-dff/gpio.h
D src/mainboard/adi/rcc-dff/irq_tables.c
D src/mainboard/adi/rcc-dff/irqroute.c
D src/mainboard/adi/rcc-dff/irqroute.h
D src/mainboard/adi/rcc-dff/romstage.c
D src/mainboard/adi/rcc-dff/thermal.h
D src/mainboard/esd/Kconfig
D src/mainboard/esd/Kconfig.name
D src/mainboard/esd/atom15/Kconfig
D src/mainboard/esd/atom15/Kconfig.name
D src/mainboard/esd/atom15/Makefile.inc
D src/mainboard/esd/atom15/acpi/ec.asl
D src/mainboard/esd/atom15/acpi/mainboard.asl
D src/mainboard/esd/atom15/acpi/superio.asl
D src/mainboard/esd/atom15/acpi_tables.c
D src/mainboard/esd/atom15/board_info.txt
D src/mainboard/esd/atom15/cmos.layout
D src/mainboard/esd/atom15/devicetree.cb
D src/mainboard/esd/atom15/dsdt.asl
D src/mainboard/esd/atom15/fadt.c
D src/mainboard/esd/atom15/gpio.c
D src/mainboard/esd/atom15/irqroute.c
D src/mainboard/esd/atom15/irqroute.h
D src/mainboard/esd/atom15/mainboard.c
D src/mainboard/esd/atom15/romstage.c
D src/mainboard/intel/bakersport_fsp/Kconfig
D src/mainboard/intel/bakersport_fsp/Kconfig.name
D src/mainboard/intel/bakersport_fsp/board_info.txt
D src/mainboard/intel/bayleybay_fsp/Kconfig
D src/mainboard/intel/bayleybay_fsp/Kconfig.name
D src/mainboard/intel/bayleybay_fsp/Makefile.inc
D src/mainboard/intel/bayleybay_fsp/acpi/ec.asl
D src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl
D src/mainboard/intel/bayleybay_fsp/acpi/superio.asl
D src/mainboard/intel/bayleybay_fsp/acpi_tables.c
D src/mainboard/intel/bayleybay_fsp/board_info.txt
D src/mainboard/intel/bayleybay_fsp/chromeos.fmd
D src/mainboard/intel/bayleybay_fsp/cmos.layout
D src/mainboard/intel/bayleybay_fsp/devicetree.cb
D src/mainboard/intel/bayleybay_fsp/dsdt.asl
D src/mainboard/intel/bayleybay_fsp/fadt.c
D src/mainboard/intel/bayleybay_fsp/gpio.c
D src/mainboard/intel/bayleybay_fsp/irqroute.c
D src/mainboard/intel/bayleybay_fsp/irqroute.h
D src/mainboard/intel/bayleybay_fsp/mainboard.c
D src/mainboard/intel/bayleybay_fsp/romstage.c
D src/mainboard/intel/bayleybay_fsp/thermal.h
D src/mainboard/intel/camelbackmountain_fsp/Kconfig
D src/mainboard/intel/camelbackmountain_fsp/Kconfig.name
D src/mainboard/intel/camelbackmountain_fsp/Makefile.inc
D src/mainboard/intel/camelbackmountain_fsp/acpi/mainboard.asl
D src/mainboard/intel/camelbackmountain_fsp/acpi/platform.asl
D src/mainboard/intel/camelbackmountain_fsp/acpi_tables.c
D src/mainboard/intel/camelbackmountain_fsp/board_info.txt
D src/mainboard/intel/camelbackmountain_fsp/cmos.layout
D src/mainboard/intel/camelbackmountain_fsp/devicetree.cb
D src/mainboard/intel/camelbackmountain_fsp/dsdt.asl
D src/mainboard/intel/camelbackmountain_fsp/fadt.c
D src/mainboard/intel/camelbackmountain_fsp/irqroute.c
D src/mainboard/intel/camelbackmountain_fsp/irqroute.h
D src/mainboard/intel/camelbackmountain_fsp/mainboard.c
D src/mainboard/intel/camelbackmountain_fsp/romstage.c
D src/mainboard/intel/cougar_canyon2/Kconfig
D src/mainboard/intel/cougar_canyon2/Kconfig.name
D src/mainboard/intel/cougar_canyon2/acpi/ec.asl
D src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl
D src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl
D src/mainboard/intel/cougar_canyon2/acpi/platform.asl
D src/mainboard/intel/cougar_canyon2/acpi/superio.asl
D src/mainboard/intel/cougar_canyon2/acpi_tables.c
D src/mainboard/intel/cougar_canyon2/board_info.txt
D src/mainboard/intel/cougar_canyon2/cmos.layout
D src/mainboard/intel/cougar_canyon2/devicetree.cb
D src/mainboard/intel/cougar_canyon2/dsdt.asl
D src/mainboard/intel/cougar_canyon2/gpio.h
D src/mainboard/intel/cougar_canyon2/hda_verb.c
D src/mainboard/intel/cougar_canyon2/mainboard.c
D src/mainboard/intel/cougar_canyon2/mainboard_smi.c
D src/mainboard/intel/cougar_canyon2/romstage.c
D src/mainboard/intel/cougar_canyon2/thermal.h
D src/mainboard/intel/littleplains/Kconfig
D src/mainboard/intel/littleplains/Kconfig.name
D src/mainboard/intel/littleplains/Makefile.inc
D src/mainboard/intel/littleplains/acpi/ec.asl
D src/mainboard/intel/littleplains/acpi/mainboard.asl
D src/mainboard/intel/littleplains/acpi/platform.asl
D src/mainboard/intel/littleplains/acpi/superio.asl
D src/mainboard/intel/littleplains/acpi/thermal.asl
D src/mainboard/intel/littleplains/acpi_tables.c
D src/mainboard/intel/littleplains/board_info.txt
D src/mainboard/intel/littleplains/cmos.layout
D src/mainboard/intel/littleplains/config_seabios
D src/mainboard/intel/littleplains/devicetree.cb
D src/mainboard/intel/littleplains/dsdt.asl
D src/mainboard/intel/littleplains/fadt.c
D src/mainboard/intel/littleplains/gpio.h
D src/mainboard/intel/littleplains/irq_tables.c
D src/mainboard/intel/littleplains/irqroute.c
D src/mainboard/intel/littleplains/irqroute.h
D src/mainboard/intel/littleplains/romstage.c
D src/mainboard/intel/littleplains/thermal.h
D src/mainboard/intel/minnowmax/Kconfig
D src/mainboard/intel/minnowmax/Kconfig.name
D src/mainboard/intel/minnowmax/Makefile.inc
D src/mainboard/intel/minnowmax/acpi/ec.asl
D src/mainboard/intel/minnowmax/acpi/mainboard.asl
D src/mainboard/intel/minnowmax/acpi/superio.asl
D src/mainboard/intel/minnowmax/acpi_tables.c
D src/mainboard/intel/minnowmax/board_info.txt
D src/mainboard/intel/minnowmax/cmos.layout
D src/mainboard/intel/minnowmax/devicetree.cb
D src/mainboard/intel/minnowmax/dsdt.asl
D src/mainboard/intel/minnowmax/fadt.c
D src/mainboard/intel/minnowmax/gpio.c
D src/mainboard/intel/minnowmax/irqroute.c
D src/mainboard/intel/minnowmax/irqroute.h
D src/mainboard/intel/minnowmax/mainboard.c
D src/mainboard/intel/minnowmax/romstage.c
D src/mainboard/intel/mohonpeak/Kconfig
D src/mainboard/intel/mohonpeak/Kconfig.name
D src/mainboard/intel/mohonpeak/Makefile.inc
D src/mainboard/intel/mohonpeak/acpi/ec.asl
D src/mainboard/intel/mohonpeak/acpi/mainboard.asl
D src/mainboard/intel/mohonpeak/acpi/platform.asl
D src/mainboard/intel/mohonpeak/acpi/superio.asl
D src/mainboard/intel/mohonpeak/acpi/thermal.asl
D src/mainboard/intel/mohonpeak/acpi_tables.c
D src/mainboard/intel/mohonpeak/board_info.txt
D src/mainboard/intel/mohonpeak/cmos.layout
D src/mainboard/intel/mohonpeak/config_seabios
D src/mainboard/intel/mohonpeak/devicetree.cb
D src/mainboard/intel/mohonpeak/dsdt.asl
D src/mainboard/intel/mohonpeak/fadt.c
D src/mainboard/intel/mohonpeak/gpio.h
D src/mainboard/intel/mohonpeak/irq_tables.c
D src/mainboard/intel/mohonpeak/irqroute.c
D src/mainboard/intel/mohonpeak/irqroute.h
D src/mainboard/intel/mohonpeak/romstage.c
D src/mainboard/intel/mohonpeak/thermal.h
D src/mainboard/intel/stargo2/Kconfig
D src/mainboard/intel/stargo2/Kconfig.name
D src/mainboard/intel/stargo2/acpi/ec.asl
D src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl
D src/mainboard/intel/stargo2/acpi/mainboard.asl
D src/mainboard/intel/stargo2/acpi/platform.asl
D src/mainboard/intel/stargo2/acpi/superio.asl
D src/mainboard/intel/stargo2/acpi_tables.c
D src/mainboard/intel/stargo2/board_info.txt
D src/mainboard/intel/stargo2/cmos.layout
D src/mainboard/intel/stargo2/devicetree.cb
D src/mainboard/intel/stargo2/dsdt.asl
D src/mainboard/intel/stargo2/gpio.h
D src/mainboard/intel/stargo2/mainboard.c
D src/mainboard/intel/stargo2/mainboard_smi.c
D src/mainboard/intel/stargo2/romstage.c
D src/mainboard/intel/stargo2/thermal.h
D src/mainboard/siemens/mc_bdx1/Kconfig
D src/mainboard/siemens/mc_bdx1/Kconfig.name
D src/mainboard/siemens/mc_bdx1/Makefile.inc
D src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl
D src/mainboard/siemens/mc_bdx1/acpi/platform.asl
D src/mainboard/siemens/mc_bdx1/acpi_tables.c
D src/mainboard/siemens/mc_bdx1/board_info.txt
D src/mainboard/siemens/mc_bdx1/cmos.layout
D src/mainboard/siemens/mc_bdx1/devicetree.cb
D src/mainboard/siemens/mc_bdx1/dsdt.asl
D src/mainboard/siemens/mc_bdx1/fadt.c
D src/mainboard/siemens/mc_bdx1/irqroute.c
D src/mainboard/siemens/mc_bdx1/irqroute.h
D src/mainboard/siemens/mc_bdx1/mainboard.c
D src/mainboard/siemens/mc_bdx1/romstage.c
D src/mainboard/siemens/mc_tcu3/Kconfig
D src/mainboard/siemens/mc_tcu3/Kconfig.name
D src/mainboard/siemens/mc_tcu3/Makefile.inc
D src/mainboard/siemens/mc_tcu3/acpi/ec.asl
D src/mainboard/siemens/mc_tcu3/acpi/mainboard.asl
D src/mainboard/siemens/mc_tcu3/acpi/superio.asl
D src/mainboard/siemens/mc_tcu3/acpi_tables.c
D src/mainboard/siemens/mc_tcu3/board_info.txt
D src/mainboard/siemens/mc_tcu3/cmos.layout
D src/mainboard/siemens/mc_tcu3/devicetree.cb
D src/mainboard/siemens/mc_tcu3/dsdt.asl
D src/mainboard/siemens/mc_tcu3/fadt.c
D src/mainboard/siemens/mc_tcu3/gpio.c
D src/mainboard/siemens/mc_tcu3/hwinfo.hex
D src/mainboard/siemens/mc_tcu3/hwinfo10.hex
D src/mainboard/siemens/mc_tcu3/hwinfo12.hex
D src/mainboard/siemens/mc_tcu3/hwinfo15.hex
D src/mainboard/siemens/mc_tcu3/hwinfo19.hex
D src/mainboard/siemens/mc_tcu3/irqroute.c
D src/mainboard/siemens/mc_tcu3/irqroute.h
D src/mainboard/siemens/mc_tcu3/lcd_panel.c
D src/mainboard/siemens/mc_tcu3/lcd_panel.h
D src/mainboard/siemens/mc_tcu3/mainboard.c
D src/mainboard/siemens/mc_tcu3/ptn3460.c
D src/mainboard/siemens/mc_tcu3/ptn3460.h
D src/mainboard/siemens/mc_tcu3/romstage.c
D src/mainboard/siemens/mc_tcu3/thermal.h
D src/northbridge/intel/fsp_rangeley/Kconfig
D src/northbridge/intel/fsp_rangeley/Makefile.inc
D src/northbridge/intel/fsp_rangeley/acpi.c
D src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
D src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
D src/northbridge/intel/fsp_rangeley/chip.h
D src/northbridge/intel/fsp_rangeley/fsp/Kconfig
D src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc
D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
D src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
D src/northbridge/intel/fsp_rangeley/northbridge.c
D src/northbridge/intel/fsp_rangeley/northbridge.h
D src/northbridge/intel/fsp_rangeley/port_access.c
D src/northbridge/intel/fsp_rangeley/raminit.c
D src/northbridge/intel/fsp_rangeley/udelay.c
D src/northbridge/intel/fsp_sandybridge/Kconfig
D src/northbridge/intel/fsp_sandybridge/Makefile.inc
D src/northbridge/intel/fsp_sandybridge/acpi.c
D src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
D src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
D src/northbridge/intel/fsp_sandybridge/chip.h
D src/northbridge/intel/fsp_sandybridge/early_init.c
D src/northbridge/intel/fsp_sandybridge/finalize.c
D src/northbridge/intel/fsp_sandybridge/fsp/Kconfig
D src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc
D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h
D src/northbridge/intel/fsp_sandybridge/gma.c
D src/northbridge/intel/fsp_sandybridge/gma.h
D src/northbridge/intel/fsp_sandybridge/northbridge.c
D src/northbridge/intel/fsp_sandybridge/northbridge.h
D src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h
D src/northbridge/intel/fsp_sandybridge/ram_calc.c
D src/northbridge/intel/fsp_sandybridge/raminit.c
D src/northbridge/intel/fsp_sandybridge/raminit.h
D src/northbridge/intel/fsp_sandybridge/report_platform.c
D src/northbridge/intel/fsp_sandybridge/udelay.c
D src/soc/intel/fsp_baytrail/Kconfig
D src/soc/intel/fsp_baytrail/Makefile.inc
D src/soc/intel/fsp_baytrail/acpi.c
D src/soc/intel/fsp_baytrail/acpi/cpu.asl
D src/soc/intel/fsp_baytrail/acpi/device_nvs.asl
D src/soc/intel/fsp_baytrail/acpi/globalnvs.asl
D src/soc/intel/fsp_baytrail/acpi/gpio.asl
D src/soc/intel/fsp_baytrail/acpi/irq_helper.h
D src/soc/intel/fsp_baytrail/acpi/irqlinks.asl
D src/soc/intel/fsp_baytrail/acpi/irqroute.asl
D src/soc/intel/fsp_baytrail/acpi/lpc.asl
D src/soc/intel/fsp_baytrail/acpi/lpe.asl
D src/soc/intel/fsp_baytrail/acpi/lpss.asl
D src/soc/intel/fsp_baytrail/acpi/platform.asl
D src/soc/intel/fsp_baytrail/acpi/scc.asl
D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
D src/soc/intel/fsp_baytrail/acpi/southcluster.asl
D src/soc/intel/fsp_baytrail/acpi/usb.asl
D src/soc/intel/fsp_baytrail/acpi/xhci.asl
D src/soc/intel/fsp_baytrail/bootblock/bootblock.c
D src/soc/intel/fsp_baytrail/chip.c
D src/soc/intel/fsp_baytrail/chip.h
D src/soc/intel/fsp_baytrail/cpu.c
D src/soc/intel/fsp_baytrail/fsp/Kconfig
D src/soc/intel/fsp_baytrail/fsp/Makefile.inc
D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
D src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
D src/soc/intel/fsp_baytrail/gfx.c
D src/soc/intel/fsp_baytrail/gpio.c
D src/soc/intel/fsp_baytrail/i2c.c
D src/soc/intel/fsp_baytrail/include/soc/acpi.h
D src/soc/intel/fsp_baytrail/include/soc/baytrail.h
D src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
D src/soc/intel/fsp_baytrail/include/soc/ehci.h
D src/soc/intel/fsp_baytrail/include/soc/gfx.h
D src/soc/intel/fsp_baytrail/include/soc/gpio.h
D src/soc/intel/fsp_baytrail/include/soc/i2c.h
D src/soc/intel/fsp_baytrail/include/soc/iomap.h
D src/soc/intel/fsp_baytrail/include/soc/iosf.h
D src/soc/intel/fsp_baytrail/include/soc/irq.h
D src/soc/intel/fsp_baytrail/include/soc/lpc.h
D src/soc/intel/fsp_baytrail/include/soc/msr.h
D src/soc/intel/fsp_baytrail/include/soc/nvm.h
D src/soc/intel/fsp_baytrail/include/soc/nvs.h
D src/soc/intel/fsp_baytrail/include/soc/pattrs.h
D src/soc/intel/fsp_baytrail/include/soc/pci_devs.h
D src/soc/intel/fsp_baytrail/include/soc/pcie.h
D src/soc/intel/fsp_baytrail/include/soc/pmc.h
D src/soc/intel/fsp_baytrail/include/soc/ramstage.h
D src/soc/intel/fsp_baytrail/include/soc/reset.h
D src/soc/intel/fsp_baytrail/include/soc/romstage.h
D src/soc/intel/fsp_baytrail/include/soc/smm.h
D src/soc/intel/fsp_baytrail/include/soc/spi.h
D src/soc/intel/fsp_baytrail/include/soc/xhci.h
D src/soc/intel/fsp_baytrail/iosf.c
D src/soc/intel/fsp_baytrail/lpe.c
D src/soc/intel/fsp_baytrail/lpss.c
D src/soc/intel/fsp_baytrail/memmap.c
D src/soc/intel/fsp_baytrail/northcluster.c
D src/soc/intel/fsp_baytrail/nvm.c
D src/soc/intel/fsp_baytrail/placeholders.c
D src/soc/intel/fsp_baytrail/pmutil.c
D src/soc/intel/fsp_baytrail/ramstage.c
D src/soc/intel/fsp_baytrail/reset.c
D src/soc/intel/fsp_baytrail/romstage/Makefile.inc
D src/soc/intel/fsp_baytrail/romstage/pmc.c
D src/soc/intel/fsp_baytrail/romstage/report_platform.c
D src/soc/intel/fsp_baytrail/romstage/romstage.c
D src/soc/intel/fsp_baytrail/romstage/uart.c
D src/soc/intel/fsp_baytrail/smihandler.c
D src/soc/intel/fsp_baytrail/smm.c
D src/soc/intel/fsp_baytrail/southcluster.c
D src/soc/intel/fsp_baytrail/spi.c
D src/soc/intel/fsp_baytrail/tsc_freq.c
D src/soc/intel/fsp_broadwell_de/Kconfig
D src/soc/intel/fsp_broadwell_de/Makefile.inc
D src/soc/intel/fsp_broadwell_de/acpi.c
D src/soc/intel/fsp_broadwell_de/acpi/irq_helper.h
D src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl
D src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl
D src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
D src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl
D src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl
D src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c
D src/soc/intel/fsp_broadwell_de/chip.c
D src/soc/intel/fsp_broadwell_de/chip.h
D src/soc/intel/fsp_broadwell_de/cpu.c
D src/soc/intel/fsp_broadwell_de/fsp/Kconfig
D src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc
D src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
D src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h
D src/soc/intel/fsp_broadwell_de/include/soc/acpi.h
D src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
D src/soc/intel/fsp_broadwell_de/include/soc/iomap.h
D src/soc/intel/fsp_broadwell_de/include/soc/irq.h
D src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
D src/soc/intel/fsp_broadwell_de/include/soc/msr.h
D src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h
D src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
D src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h
D src/soc/intel/fsp_broadwell_de/include/soc/reset.h
D src/soc/intel/fsp_broadwell_de/include/soc/romstage.h
D src/soc/intel/fsp_broadwell_de/include/soc/smbus.h
D src/soc/intel/fsp_broadwell_de/memmap.c
D src/soc/intel/fsp_broadwell_de/northcluster.c
D src/soc/intel/fsp_broadwell_de/ramstage.c
D src/soc/intel/fsp_broadwell_de/reset.c
D src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc
D src/soc/intel/fsp_broadwell_de/romstage/romstage.c
D src/soc/intel/fsp_broadwell_de/smbus.c
D src/soc/intel/fsp_broadwell_de/smbus_common.c
D src/soc/intel/fsp_broadwell_de/southcluster.c
D src/soc/intel/fsp_broadwell_de/spi.c
D src/southbridge/intel/fsp_bd82x6x/Kconfig
D src/southbridge/intel/fsp_bd82x6x/Makefile.inc
D src/southbridge/intel/fsp_bd82x6x/acpi/audio.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/irqlinks.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/pcie.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/pcie_port.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/sata.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/sleepstates.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/smbus.asl
D src/southbridge/intel/fsp_bd82x6x/acpi/usb.asl
D src/southbridge/intel/fsp_bd82x6x/azalia.c
D src/southbridge/intel/fsp_bd82x6x/bootblock.c
D src/southbridge/intel/fsp_bd82x6x/chip.h
D src/southbridge/intel/fsp_bd82x6x/early_init.c
D src/southbridge/intel/fsp_bd82x6x/early_me.c
D src/southbridge/intel/fsp_bd82x6x/early_smbus.c
D src/southbridge/intel/fsp_bd82x6x/early_spi.c
D src/southbridge/intel/fsp_bd82x6x/early_usb.c
D src/southbridge/intel/fsp_bd82x6x/elog.c
D src/southbridge/intel/fsp_bd82x6x/finalize.c
D src/southbridge/intel/fsp_bd82x6x/gpio.c
D src/southbridge/intel/fsp_bd82x6x/gpio.h
D src/southbridge/intel/fsp_bd82x6x/lpc.c
D src/southbridge/intel/fsp_bd82x6x/me.c
D src/southbridge/intel/fsp_bd82x6x/me.h
D src/southbridge/intel/fsp_bd82x6x/me_8.x.c
D src/southbridge/intel/fsp_bd82x6x/me_status.c
D src/southbridge/intel/fsp_bd82x6x/nvs.h
D src/southbridge/intel/fsp_bd82x6x/pch.c
D src/southbridge/intel/fsp_bd82x6x/pch.h
D src/southbridge/intel/fsp_bd82x6x/reset.c
D src/southbridge/intel/fsp_bd82x6x/sata.c
D src/southbridge/intel/fsp_bd82x6x/smi.c
D src/southbridge/intel/fsp_bd82x6x/smihandler.c
D src/southbridge/intel/fsp_bd82x6x/southbridge_pci_devs.h
D src/southbridge/intel/fsp_bd82x6x/watchdog.c
D src/southbridge/intel/fsp_i89xx/Kconfig
D src/southbridge/intel/fsp_i89xx/Makefile.inc
D src/southbridge/intel/fsp_i89xx/acpi/globalnvs.asl
D src/southbridge/intel/fsp_i89xx/acpi/irqlinks.asl
D src/southbridge/intel/fsp_i89xx/acpi/lpc.asl
D src/southbridge/intel/fsp_i89xx/acpi/pch.asl
D src/southbridge/intel/fsp_i89xx/acpi/pcie.asl
D src/southbridge/intel/fsp_i89xx/acpi/pcie_port.asl
D src/southbridge/intel/fsp_i89xx/acpi/platform.asl
D src/southbridge/intel/fsp_i89xx/acpi/sata.asl
D src/southbridge/intel/fsp_i89xx/acpi/sleepstates.asl
D src/southbridge/intel/fsp_i89xx/acpi/smbus.asl
D src/southbridge/intel/fsp_i89xx/acpi/usb.asl
D src/southbridge/intel/fsp_i89xx/bootblock.c
D src/southbridge/intel/fsp_i89xx/chip.h
D src/southbridge/intel/fsp_i89xx/early_init.c
D src/southbridge/intel/fsp_i89xx/early_me.c
D src/southbridge/intel/fsp_i89xx/early_smbus.c
D src/southbridge/intel/fsp_i89xx/early_spi.c
D src/southbridge/intel/fsp_i89xx/early_usb.c
D src/southbridge/intel/fsp_i89xx/elog.c
D src/southbridge/intel/fsp_i89xx/finalize.c
D src/southbridge/intel/fsp_i89xx/gpio.c
D src/southbridge/intel/fsp_i89xx/gpio.h
D src/southbridge/intel/fsp_i89xx/lpc.c
D src/southbridge/intel/fsp_i89xx/me.c
D src/southbridge/intel/fsp_i89xx/me.h
D src/southbridge/intel/fsp_i89xx/me_8.x.c
D src/southbridge/intel/fsp_i89xx/me_status.c
D src/southbridge/intel/fsp_i89xx/nvs.h
D src/southbridge/intel/fsp_i89xx/pch.c
D src/southbridge/intel/fsp_i89xx/pch.h
D src/southbridge/intel/fsp_i89xx/reset.c
D src/southbridge/intel/fsp_i89xx/romstage.c
D src/southbridge/intel/fsp_i89xx/romstage.h
D src/southbridge/intel/fsp_i89xx/sata.c
D src/southbridge/intel/fsp_i89xx/smbus.h
D src/southbridge/intel/fsp_i89xx/smi.c
D src/southbridge/intel/fsp_i89xx/smihandler.c
D src/southbridge/intel/fsp_i89xx/southbridge_pci_devs.h
D src/southbridge/intel/fsp_i89xx/watchdog.c
D src/southbridge/intel/fsp_rangeley/Kconfig
D src/southbridge/intel/fsp_rangeley/Makefile.inc
D src/southbridge/intel/fsp_rangeley/acpi.c
D src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl
D src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h
D src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl
D src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl
D src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
D src/southbridge/intel/fsp_rangeley/acpi/pcie.asl
D src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl
D src/southbridge/intel/fsp_rangeley/acpi/sata.asl
D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl
D src/southbridge/intel/fsp_rangeley/acpi/smbus.asl
D src/southbridge/intel/fsp_rangeley/acpi/soc.asl
D src/southbridge/intel/fsp_rangeley/acpi/usb.asl
D src/southbridge/intel/fsp_rangeley/chip.h
D src/southbridge/intel/fsp_rangeley/early_init.c
D src/southbridge/intel/fsp_rangeley/early_smbus.c
D src/southbridge/intel/fsp_rangeley/early_spi.c
D src/southbridge/intel/fsp_rangeley/early_usb.c
D src/southbridge/intel/fsp_rangeley/gpio.c
D src/southbridge/intel/fsp_rangeley/gpio.h
D src/southbridge/intel/fsp_rangeley/irq.h
D src/southbridge/intel/fsp_rangeley/lpc.c
D src/southbridge/intel/fsp_rangeley/nvs.h
D src/southbridge/intel/fsp_rangeley/pci_devs.h
D src/southbridge/intel/fsp_rangeley/reset.c
D src/southbridge/intel/fsp_rangeley/romstage.c
D src/southbridge/intel/fsp_rangeley/romstage.h
D src/southbridge/intel/fsp_rangeley/sata.c
D src/southbridge/intel/fsp_rangeley/smbus.c
D src/southbridge/intel/fsp_rangeley/smbus.h
D src/southbridge/intel/fsp_rangeley/soc.c
D src/southbridge/intel/fsp_rangeley/soc.h
D src/southbridge/intel/fsp_rangeley/spi.c
D src/southbridge/intel/fsp_rangeley/watchdog.c
M src/vendorcode/intel/Kconfig
M src/vendorcode/intel/Makefile.inc
D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
D src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h
D src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h
D src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c
D src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fsp.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspapi.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspbootmode.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspffs.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspfv.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fsphob.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspinfoheader.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspplatform.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspsupport.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fsptypes.h
D src/vendorcode/intel/fsp1_0/broadwell_de/include/fspvpd.h
D src/vendorcode/intel/fsp1_0/broadwell_de/srx/fspsupport.c
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspapi.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspffs.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspfv.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsphob.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspinfoheader.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspplatform.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsptypes.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/mem_config.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/peifsp.h
D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/srx/fsphob.c
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsp_vpd.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspapi.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspffs.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspfv.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsphob.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspinfoheader.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspplatform.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsptypes.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/mem_config.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/peifsp.h
D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/srx/fsphob.c
D src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h
D src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h
D src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c
D src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c
M util/board_status/to-wiki/towiki.sh
575 files changed, 2 insertions(+), 71,025 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/18891/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ia032f950f8dc9b92f5e96368e57f513ba5598aa2
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Adurb Akhbar
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