[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use C entry code for MTRR programming

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/18923 )

Change subject: soc/intel/skylake: Use C entry code for MTRR programming
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soc/intel/skylake: Use C entry code for MTRR programming

Make skylake cache as ram SPI mapped MTRR programming
align with apollolake code.

Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/cache_as_ram.S
M src/soc/intel/skylake/bootblock/cpu.c
3 files changed, 31 insertions(+), 39 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/18923/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>