[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Create API to read SPI Flash MMIO register

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/18921 )

Change subject: soc/intel/skylake: Create API to read SPI Flash MMIO register
......................................................................

soc/intel/skylake: Create API to read SPI Flash MMIO register

Need this patch to get BIOS ROM size for MTRR program.

Change-Id: I43400aa7204c27c73fd70e93027005d19def56ac
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/flash_controller.c
M src/soc/intel/skylake/include/soc/flash_controller.h
M src/soc/intel/skylake/include/soc/spi.h
3 files changed, 19 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/18921/1

diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 476a08c..f30ecd8 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -127,6 +127,17 @@
 	return min(SPI_FDATA_BYTES, buf_len);
 }
 
+/* Read register from the SPI flash controller. 'reg' is the register offset. */
+static uint32_t _spi_flash_ctrlr_reg_read(uint8_t *spi_bar, uint16_t reg)
+{
+	return read32(spi_bar + reg);
+}
+
+uint32_t spi_flash_ctrlr_reg_read(uint16_t reg)
+{
+	return _spi_flash_ctrlr_reg_read(get_spi_bar(), reg);
+}
+
 static size_t spi_get_flash_size(pch_spi_flash_regs *spi_bar)
 {
 	uint32_t flcomp;
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 25e7734..39b36e6 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -30,6 +30,8 @@
 
 void spi_flash_init(void);
 
+uint32_t spi_flash_ctrlr_reg_read(uint16_t reg);
+
 #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
 static u8 readb_(const void *addr)
 {
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h
index a92b78d..9cbcb11 100644
--- a/src/soc/intel/skylake/include/soc/spi.h
+++ b/src/soc/intel/skylake/include/soc/spi.h
@@ -78,6 +78,12 @@
 
 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
 
+#define SPIBAR_BFPREG		0x00
+#define  SPIBAR_BFPREG_PRB_MASK	(0x7fff)
+#define  SPIBAR_BFPREG_PRL_SHIFT	(16)
+#define  SPIBAR_BFPREG_PRL_MASK	(0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
+#define  SPIBAR_BFPREG_SBRS		(1 << 31)
+
 #define SPIBAR_HSFS		0x04	 /* SPI hardware sequence status */
 #define  SPIBAR_HSFS_FLOCKDN	(1 << 15)/* Flash Configuration Lock-Down */
 #define  SPIBAR_HSFS_SCIP	(1 << 5) /* SPI Cycle In Progress */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I43400aa7204c27c73fd70e93027005d19def56ac
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>