[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Create API to get cache size

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/18922 )

Change subject: soc/intel/skylake: Create API to get cache size
......................................................................

soc/intel/skylake: Create API to get cache size

Calculate cache size based on SPI Flash MMIO offset 0x00 to
get BIOS region start and end.

Change-Id: I024e0a9e4ee33794a7ea91bc57c5ee6673825e47
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
A src/soc/intel/skylake/include/soc/mmap_boot.h
A src/soc/intel/skylake/mmap_boot.c
2 files changed, 129 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/18922/1

diff --git a/src/soc/intel/skylake/include/soc/mmap_boot.h b/src/soc/intel/skylake/include/soc/mmap_boot.h
new file mode 100644
index 0000000..7cf02f8
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/mmap_boot.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_SKYLAKE_MMAP_BOOT_H__
+#define __SOC_SKYLAKE_MMAP_BOOT_H__
+
+size_t get_bios_size(void);
+
+#endif /* __SOC_SKYLAKE_MMAP_BOOT_H__ */
diff --git a/src/soc/intel/skylake/mmap_boot.c b/src/soc/intel/skylake/mmap_boot.c
new file mode 100644
index 0000000..2c84ebe
--- /dev/null
+++ b/src/soc/intel/skylake/mmap_boot.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <boot_device.h>
+#include <commonlib/region.h>
+#include <soc/flash_controller.h>
+#include <soc/mmap_boot.h>
+#include <soc/spi.h>
+
+/*
+ * BIOS region on the flash is mapped right below 4GiB in the address
+ * space.
+ *
+ *                                                            +----------------+ 0
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                                                            |                |
+ *                  +------------+                            |                |
+ *                  |    IFD     |                            |                |
+ * bios_start +---> +------------+--------------------------> +----------------+ 4GiB - bios_size
+ *     ^            |            |              ^             |                |
+ *     |            |            |              |             |                |
+ *     |            |            |       bios_mapped_size     |      BIOS      |
+ *     |            |    BIOS    |              |             |                |
+ * bios_size        |            |              |             |                |
+ *     |            |            |              |             |                |
+ *     v            |            |              v             |                |
+ * bios_end   +---> +------------+                            +----------------+ 4GiB
+ *                  | Device ext |
+ *                  +------------+
+ *
+ */
+
+static size_t bios_start CAR_GLOBAL;
+static size_t bios_size CAR_GLOBAL;
+
+static struct mem_region_device shadow_dev CAR_GLOBAL;
+static struct xlate_region_device real_dev CAR_GLOBAL;
+
+static void bios_mmap_init(void)
+{
+	size_t size;
+
+	size = car_get_var(bios_size);
+
+	/* If bios_size is initialized, then bail out. */
+	if (size != 0)
+		return;
+
+	size_t start, bios_end, bios_mapped_size;
+	uintptr_t base;
+
+	/*
+	 * BIOS_BFPREG provides info about BIOS Flash Primary Region
+	 * Base and Limit.
+	 * Base and Limit fields are in units of 4KiB.
+	 */
+	uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BFPREG);
+
+	start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
+	bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
+		     SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
+	size = bios_end - start;
+
+	/* BIOS region is mapped right below 4G. */
+	base = 4ULL * GiB - size;
+
+	struct mem_region_device *shadow_dev_ptr;
+	struct xlate_region_device *real_dev_ptr;
+	shadow_dev_ptr = car_get_var_ptr(&shadow_dev);
+	real_dev_ptr = car_get_var_ptr(&real_dev);
+
+	mem_region_device_ro_init(shadow_dev_ptr, (void *)base,
+			       bios_mapped_size);
+
+	xlate_region_device_ro_init(real_dev_ptr, &shadow_dev_ptr->rdev,
+				 start, bios_mapped_size,
+				 CONFIG_ROM_SIZE);
+
+	car_set_var(bios_start, start);
+	car_set_var(bios_size, size);
+}
+
+size_t get_bios_size(void)
+{
+	bios_mmap_init();
+	return car_get_var(bios_size);
+}

-- 
To view, visit https://review.coreboot.org/18922
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I024e0a9e4ee33794a7ea91bc57c5ee6673825e47
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>