[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18381 )

Change subject: soc/intel/common/block: Add cache as ram init and teardown code
......................................................................


Patch Set 29:

(1 comment)

https://review.coreboot.org/#/c/18381/29/src/soc/intel/common/block/cpu/car/cache_as_ram.S
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

Line 430: 	jne	car_init_done
> What is this about? 768KiB uses 2 MTRR register to program the CAR area. An
I have done some study on this and as per my opinion, introducing C support like APL will help to only cache BIOS region unlike entire Flash chip we used to do in SKL. 

Basically we are trying to address 2 problem.

1. Ensure SPI mapped MTRR ranges are not yet programmed if yes, then just skip it.

2. Program SPI mapped range into Code MTRR after reading SPI size. In order to get rom_size, we have use primary region base and limit to get "only" BIOS region.

But the only concern i have with this piece of C code is that, its getting executed bit late compare to where its done today. Which mean we are running some early code w/o cache although those are simple register programming.


-- 
To view, visit https://review.coreboot.org/18381
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: comment
Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Gerrit-PatchSet: 29
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
Gerrit-HasComments: Yes