[coreboot-gerrit] Change in coreboot[master]: cpu/x86: add a barrier with timeout

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18107 )

Change subject: cpu/x86: add a barrier with timeout
......................................................................


cpu/x86: add a barrier with timeout

In case something goes wrong on one of the
cpus, add the ability to use a barrier with
timeout so that other cpus don't wait forever.
Remove static from barrier wait and release.

BUG=chrome-os-partner:59875
BRANCH=reef
TEST=None

Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
Reviewed-on: https://review.coreboot.org/18107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/mp.h
2 files changed, 35 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved



diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 57a5648..61f153e 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -138,14 +138,37 @@
 /* Keep track of APIC and device structure for each CPU. */
 static struct cpu_map cpus[CONFIG_MAX_CPUS];
 
-static inline void barrier_wait(atomic_t *b)
+inline void barrier_wait(atomic_t *b)
 {
 	while (atomic_read(b) == 0)
 		asm ("pause");
 	mfence();
 }
 
-static inline void release_barrier(atomic_t *b)
+/* Returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout. */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms)
+{
+	int timeout = 0;
+	struct mono_time current, end;
+
+	timer_monotonic_get(&current);
+	end = current;
+	mono_time_add_msecs(&end, timeout_ms);
+
+	while ((atomic_read(b) == 0) && (!mono_time_after(&current, &end))) {
+		timer_monotonic_get(&current);
+		asm ("pause");
+	}
+	mfence();
+
+	if (mono_time_after(&current, &end))
+		timeout = 1;
+
+	return timeout;
+}
+
+inline void release_barrier(atomic_t *b)
 {
 	mfence();
 	atomic_set(b, 1);
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index b9b4d57..0671b62 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -150,5 +150,15 @@
 void smm_initiate_relocation_parallel(void);
 /* Send SMI to self with single execution. */
 void smm_initiate_relocation(void);
+/* Make a CPU wait until the barrier is released */
+void barrier_wait(atomic_t *b);
+/*
+ * Make a CPU wait until the barrier is released, or timeout occurs
+ * returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout.
+ */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms);
+/* Release a barrier so that other CPUs waiting for that barrier can continue */
+void release_barrier(atomic_t *b);
 
 #endif /* _X86_MP_H_ */

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Timothy Pearson <tpearson at raptorengineering.com>
Gerrit-Reviewer: build bot (Jenkins)