[coreboot-gerrit] Change in coreboot[master]: drivers/intel/fsp1_1: Fix issues detected by checkpatch
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 22:13:37 CET 2017
Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/18886 )
Change subject: drivers/intel/fsp1_1: Fix issues detected by checkpatch
......................................................................
drivers/intel/fsp1_1: Fix issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
---
M src/drivers/intel/fsp1_1/fsp_gop.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/hob.c
M src/drivers/intel/fsp1_1/include/fsp/util.h
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp1_1/stack.c
7 files changed, 27 insertions(+), 29 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index 6d905b2..28ed06d 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -71,10 +71,9 @@
if (vbt_hob == NULL) {
printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
return;
- } else {
- printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
- vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
}
+ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
+ vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
framebuffer->physical_address = vbt_gop->FrameBufferBase;
framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 5ce753f..0d09483 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -45,9 +45,8 @@
fsp_ptr.u32 = fsp_base_address;
/* Check the FV signature, _FVH */
- if (fsp_ptr.fvh->Signature != 0x4856465F) {
+ if (fsp_ptr.fvh->Signature != 0x4856465F)
return (FSP_INFO_HEADER *)ERROR_NO_FV_SIG;
- }
/* Locate the file header which follows the FV header. */
fsp_ptr.u32 += fsp_ptr.fvh->ExtHeaderOffset;
@@ -65,22 +64,19 @@
/* Locate the Raw Section Header */
fsp_ptr.u32 += sizeof(EFI_FFS_FILE_HEADER);
- if (fsp_ptr.rs->Type != EFI_SECTION_RAW) {
+ if (fsp_ptr.rs->Type != EFI_SECTION_RAW)
return (FSP_INFO_HEADER *)ERROR_NO_INFO_HEADER;
- }
/* Locate the FSP INFO Header which follows the Raw Header. */
fsp_ptr.u32 += sizeof(EFI_RAW_SECTION);
/* Verify that the FSP base address.*/
- if (fsp_ptr.fih->ImageBase != fsp_base_address) {
+ if (fsp_ptr.fih->ImageBase != fsp_base_address)
return (FSP_INFO_HEADER *)ERROR_IMAGEBASE_MISMATCH;
- }
/* Verify the FSP Signature */
- if (fsp_ptr.fih->Signature != FSP_SIG) {
+ if (fsp_ptr.fih->Signature != FSP_SIG)
return (FSP_INFO_HEADER *)ERROR_INFO_HEAD_SIG_MISMATCH;
- }
/* Verify the FSP ID */
image_id = (u32 *)&fsp_ptr.fih->ImageId[0];
@@ -290,7 +286,8 @@
}
}
-size_t EFIAPI fsp_write_line(uint8_t *buffer, size_t number_of_bytes)
+__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer,
+ size_t number_of_bytes)
{
console_write_line(buffer, number_of_bytes);
return number_of_bytes;
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index c0816e9..85d0f35 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -69,7 +69,7 @@
}
/* Returns the next instance of the matched GUID HOB from the starting HOB. */
-void *get_next_guid_hob(const EFI_GUID * guid, const void *hob_start)
+void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start)
{
EFI_PEI_HOB_POINTERS hob;
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index eea0c33..32ac99e 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -92,12 +92,11 @@
extern void *FspHobListPtr;
#endif
-/* TODO: Remove the EFI types and decorations from coreboot implementations. */
-VOID * EFIAPI get_hob_list(VOID);
-VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
-VOID * EFIAPI get_first_hob(UINT16 type);
-VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
-VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+void *get_hob_list(void);
+void *get_next_hob(uint16_t type, const void *hob_start);
+void *get_first_hob(uint16_t type);
+void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_guid_hob(const EFI_GUID *guid);
/*
* Writes number_of_bytes data bytes from buffer to the console.
@@ -106,6 +105,7 @@
* If number_of_bytes is zero, don't output any data but instead wait until
* the console has output all data, then return 0.
*/
-size_t EFIAPI fsp_write_line(uint8_t *buffer, size_t number_of_bytes);
+__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer,
+ size_t number_of_bytes);
#endif /* FSP1_1_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 4b07ede..6e2efcf 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -183,7 +183,7 @@
/* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
hob_list_ptr);
- if (NULL == memory_info_hob) {
+ if (memory_info_hob == NULL) {
printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
fsp_verification_failure = 1;
} else {
@@ -205,7 +205,7 @@
* 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
* FSP_SMBIOS_MEMORY_INFO HOB verified above
*/
- if (NULL != cbmem_root) {
+ if (cbmem_root != NULL) {
printk(BIOS_DEBUG,
"7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
cbmem_root);
@@ -215,7 +215,7 @@
printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
}
hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
- if (NULL == hob_ptr.Raw) {
+ if (hob_ptr.Raw == NULL) {
printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
fsp_verification_failure =
(params->pei_data->saved_data == NULL) ? 1 : 0;
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 3933b2e..c2fc667 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -161,10 +161,10 @@
if ((params->pei_data->boot_mode != ACPI_S3)
&& (params->pei_data->data_to_save_size != 0)
&& (params->pei_data->data_to_save != NULL))
- mrc_cache_stash_data(MRC_TRAINING_DATA,
- params->fsp_version,
- params->pei_data->data_to_save,
- params->pei_data->data_to_save_size);
+ mrc_cache_stash_data(MRC_TRAINING_DATA,
+ params->fsp_version,
+ params->pei_data->data_to_save,
+ params->pei_data->data_to_save_size);
}
/* Save DIMM information */
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 059f8ba..639cf38 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -71,7 +71,8 @@
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1)
+ | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;
@@ -136,7 +137,8 @@
/* Cache the ROM as WP just below 4GiB. */
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1)
+ | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
--
To view, visit https://review.coreboot.org/18886
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Gerrit-MessageType: merged
Gerrit-Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: build bot (Jenkins)
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