[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Fix other issues detected by checkpatch
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 19:21:59 CET 2017
Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/18885 )
Change subject: soc/intel/broadwell: Fix other issues detected by checkpatch
......................................................................
soc/intel/broadwell: Fix other issues detected by checkpatch
Fix the following error and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test
TEST=None
Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
Reviewed-on: https://review.coreboot.org/18885
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/broadwell/include/soc/igd.h
M src/soc/intel/broadwell/include/soc/romstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/broadwell/spi.c
9 files changed, 51 insertions(+), 40 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h
index e7d3777..cdbee4b 100644
--- a/src/soc/intel/broadwell/include/soc/igd.h
+++ b/src/soc/intel/broadwell/include/soc/igd.h
@@ -17,4 +17,4 @@
u32 igd_get_reg_em4(void);
u32 igd_get_reg_em5(void);
-#endif /* SOC_INTEL_BROADWELL_GMA_H */
\ No newline at end of file
+#endif /* SOC_INTEL_BROADWELL_GMA_H */
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index ec733f8..eb4e097 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -29,9 +29,9 @@
void mainboard_romstage_entry(struct romstage_params *params);
void romstage_common(struct romstage_params *params);
-void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
+asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo,
uint32_t tsc_high);
-void asmlinkage romstage_after_car(void);
+asmlinkage void romstage_after_car(void);
void raminit(struct pei_data *pei_data);
void *setup_stack_and_mttrs(void);
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index dadbaff..36e34fe 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -478,7 +478,7 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */
- if (RCBA_BASE_ADDRESS < default_decode_base) {
+ if (default_decode_base > RCBA_BASE_ADDRESS) {
res = new_resource(dev, RCBA);
res->base = RCBA_BASE_ADDRESS;
res->size = 16 * 1024;
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index c919afe..73b3c2e 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -698,7 +698,7 @@
/* Check if the MBP is ready */
if (!hfs2.mbp_rdy) {
printk(BIOS_CRIT, "%s: mbp is not ready!\n",
- __FUNCTION__);
+ __func__);
path = ME_ERROR_BIOS_PATH;
}
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 3fb60e8..aff66a3 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -266,7 +266,8 @@
* In addition to D28Fx PCICFG 420h[30:29] = 11b,
* set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
*/
- pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1);
+ pci_update_config32(dev, 0x420, ~0x20000,
+ (3 << 29) | 1);
/* Configure shared resource clock gating. */
if (rp == 1 || rp == 5 || rp == 6)
@@ -385,29 +386,29 @@
/* Check Root Port Configuration. */
switch (rp) {
- case 2:
- /* Root Port 2 is disabled for all lane configurations
- * but config 00b (4x1 links). */
- if ((rpc.strpfusecfg1 >> 14) & 0x3) {
- root_port_mark_disable(dev);
- return;
- }
- break;
- case 3:
- /* Root Port 3 is disabled in config 11b (1x4 links). */
- if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
- root_port_mark_disable(dev);
- return;
- }
- break;
- case 4:
- /* Root Port 4 is disabled in configs 11b (1x4 links)
- * and 10b (2x2 links). */
- if ((rpc.strpfusecfg1 >> 14) & 0x2) {
- root_port_mark_disable(dev);
- return;
- }
- break;
+ case 2:
+ /* Root Port 2 is disabled for all lane configurations
+ * but config 00b (4x1 links). */
+ if ((rpc.strpfusecfg1 >> 14) & 0x3) {
+ root_port_mark_disable(dev);
+ return;
+ }
+ break;
+ case 3:
+ /* Root Port 3 is disabled in config 11b (1x4 links). */
+ if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
+ root_port_mark_disable(dev);
+ return;
+ }
+ break;
+ case 4:
+ /* Root Port 4 is disabled in configs 11b (1x4 links)
+ * and 10b (2x2 links). */
+ if ((rpc.strpfusecfg1 >> 14) & 0x2) {
+ root_port_mark_disable(dev);
+ return;
+ }
+ break;
}
/* Check Pin Ownership. */
@@ -487,7 +488,8 @@
if (do_aspm) {
/* Set ASPM bits in MPC2 register. */
- pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
+ pci_update_config32(dev, 0xd4, ~(0x3 << 2),
+ (1 << 4) | (0x2 << 2));
/* Set unique clock exit latency in MPC register. */
pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
@@ -552,7 +554,8 @@
pci_update_config8(dev, 0xf5, 0x0f, 0);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
+ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+ (1 << 29) | 0x10001);
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
pci_update_config32(dev, 0x200, ~0xffff, 0x001e);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1a765cb..bd63e00 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -119,7 +119,7 @@
#endif
}
-void asmlinkage romstage_after_car(void)
+asmlinkage void romstage_after_car(void)
{
/* Load the ramstage. */
run_ramstage();
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 00f1534..8a5b443 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -118,7 +118,8 @@
uint32_t pp_ctrl;
uint32_t bl_off_delay;
- reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf);
+ reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD,
+ PCI_BASE_ADDRESS_0) & ~0xf);
/* Check if backlight is enabled */
pp_ctrl = read32(reg_base + PCH_PP_CONTROL);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index a7b75d0..1ddf37a 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -224,7 +224,8 @@
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -235,7 +236,8 @@
* on the number of physical address bits supported. */
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
- params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 22a0dab..aaf3b85 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -421,7 +421,8 @@
spi_use_out(trans, 3);
return 1;
default:
- printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
+ printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n",
+ trans->type);
return -1;
}
}
@@ -533,7 +534,8 @@
return -1;
if (status & SPIS_FCERR) {
- printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
+ printk(BIOS_DEBUG,
+ "ICH SPI: Command transaction error\n");
return -1;
}
@@ -548,8 +550,8 @@
* by the SPI chip driver.
*/
if (trans.bytesout > cntlr.databytes) {
- printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
- " CONTROLLER_PAGE_LIMIT?\n");
+ printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI"
+ " chip driver use CONTROLLER_PAGE_LIMIT?\n");
return -1;
}
@@ -561,7 +563,10 @@
uint32_t data_length;
/* SPI addresses are 24 bit only */
- /* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */
+ /* http://www.intel.com/content/dam/www/public/us/en/documents/
+ * datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-
+ * n2806-j1850-j1750-datasheet.pdf
+ */
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
if (trans.bytesout)
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins)
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