[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Fix {}, () and conditional issues
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 18:57:42 CET 2017
Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/18884 )
Change subject: soc/intel/broadwell: Fix {}, () and conditional issues
......................................................................
soc/intel/broadwell: Fix {}, () and conditional issues
Fix the following errors and warnings detected by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
TEST=None
Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/pei_data.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/refcode.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/smbus_common.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
12 files changed, 74 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/18884/1
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 2675aa5..b4db21b 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -688,9 +688,8 @@
{
struct bus *cpu_bus = dev->link_list;
- if (mp_init_with_smm(cpu_bus, &mp_ops)) {
+ if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
- }
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index fc04401..fa1340f 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -530,11 +530,10 @@
/* Late init steps */
igd_cdclk_init(dev, is_broadwell);
- if (is_broadwell) {
+ if (is_broadwell)
reg_script_run_on_dev(dev, broadwell_late_init_script);
- } else {
+ else
reg_script_run_on_dev(dev, haswell_late_init_script);
- }
if (gfx_get_init_done()) {
/*
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h
index e614718..318cb88 100644
--- a/src/soc/intel/broadwell/include/soc/pei_data.h
+++ b/src/soc/intel/broadwell/include/soc/pei_data.h
@@ -86,8 +86,7 @@
uint8_t fixed_eq;
} __attribute__((packed));
-struct pei_data
-{
+struct pei_data {
uint32_t pei_version;
enum board_type board_type;
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 8de38be..dadbaff 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -114,10 +114,18 @@
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ case 1: /* INTA# */
+ int_line = config->pirqa_routing;
+ break;
+ case 2: /* INTB# */
+ int_line = config->pirqb_routing;
+ break;
+ case 3: /* INTC# */
+ int_line = config->pirqc_routing;
+ break;
+ case 4: /* INTD# */
+ int_line = config->pirqd_routing;
+ break;
}
if (!int_line)
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 800e8ba..c919afe 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -647,10 +647,8 @@
if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
return -1;
- } else {
- printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
}
-
+ printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
return 0;
}
@@ -916,9 +914,8 @@
#if CONFIG_DEBUG_INTEL_ME
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
- for (i = 0; i < mbp->header.mbp_size - 1; i++) {
+ for (i = 0; i < mbp->header.mbp_size - 1; i++)
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
- }
#endif
#define ASSIGN_FIELD_PTR(field_, val_) \
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index c4179f1..7eb548e 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -48,9 +48,8 @@
.prog = &prog,
};
- if (acpi_is_wakeup_s3()) {
+ if (acpi_is_wakeup_s3())
return load_refcode_from_cache();
- }
if (prog_locate(&prog)) {
printk(BIOS_DEBUG, "Couldn't locate reference code.\n");
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 7c74aa4..1a765cb 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -123,14 +123,15 @@
{
/* Load the ramstage. */
run_ramstage();
- while (1);
+ while (1)
+ ;
}
int get_sw_write_protect_state(void)
{
u8 status;
/* Return unprotected status if status read fails. */
- return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
+ return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
}
void __attribute__((weak)) mainboard_pre_console_init(void) {}
diff --git a/src/soc/intel/broadwell/smbus_common.c b/src/soc/intel/broadwell/smbus_common.c
index e392f40..29b7dbb 100644
--- a/src/soc/intel/broadwell/smbus_common.c
+++ b/src/soc/intel/broadwell/smbus_common.c
@@ -62,9 +62,9 @@
unsigned char global_status_register;
unsigned char byte;
- if (smbus_wait_until_ready(smbus_base) < 0) {
+ if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
+
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
@@ -86,9 +86,8 @@
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
- if (smbus_wait_until_done(smbus_base) < 0) {
+ if (smbus_wait_until_done(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
global_status_register = inb(smbus_base + SMBHSTSTAT);
@@ -97,9 +96,8 @@
/* Read results of transaction */
byte = inb(smbus_base + SMBHSTDAT0);
- if (global_status_register != (1 << 1)) {
+ if (global_status_register != (1 << 1))
return SMBUS_ERROR;
- }
return byte;
}
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index c1092b9..00f1534 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -427,7 +427,8 @@
if (!tco_sts)
return;
- if (tco_sts & (1 << 8)) { // BIOSWR
+ // BIOSWR
+ if (tco_sts & (1 << 8)) {
u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL);
if (bios_cntl & 1) {
@@ -491,7 +492,8 @@
/* IOTRAP(0) SMIC */
if (IOTRAP(0)) {
- if (!(trap_cycle & (1 << 24))) { // It's a write
+ // It's a write
+ if (!(trap_cycle & (1 << 24))) {
printk(BIOS_DEBUG, "SMI1 command\n");
data = RCBA32(0x1e18);
data &= mask;
@@ -505,7 +507,8 @@
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i = 0; i < 4; i++)
- if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ if (IOTRAP(i))
+ printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index a7fd9ec..a7b75d0 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -292,9 +292,8 @@
*/
smm_initiate_relocation();
- if (smm_reloc_params.smm_save_state_in_msrs) {
+ if (smm_reloc_params.smm_save_state_in_msrs)
printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
- }
}
/* The default SMM entry can happen in parallel or serially. If the
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index ebcf93c..22a0dab 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -367,43 +367,43 @@
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
writew_(optypes, cntlr.optype);
return 0;
- } else {
- /* The lock is on. See if what we need is on the menu. */
- uint8_t optype;
- uint16_t opcode_index;
-
- /* Write Enable is handled as atomic prefix */
- if (trans->opcode == SPI_OPCODE_WREN)
- return 0;
-
- read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
- for (opcode_index = 0; opcode_index < cntlr.menubytes;
- opcode_index++) {
- if (opmenu[opcode_index] == trans->opcode)
- break;
- }
-
- if (opcode_index == cntlr.menubytes) {
- printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
- trans->opcode);
- return -1;
- }
-
- optypes = readw_(cntlr.optype);
- optype = (optypes >> (opcode_index * 2)) & 0x3;
- if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
- optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
- trans->bytesout >= 3) {
- /* We guessed wrong earlier. Fix it up. */
- trans->type = optype;
- }
- if (optype != trans->type) {
- printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
- optype);
- return -1;
- }
- return opcode_index;
}
+
+ /* The lock is on. See if what we need is on the menu. */
+ uint8_t optype;
+ uint16_t opcode_index;
+
+ /* Write Enable is handled as atomic prefix */
+ if (trans->opcode == SPI_OPCODE_WREN)
+ return 0;
+
+ read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
+ for (opcode_index = 0; opcode_index < cntlr.menubytes;
+ opcode_index++) {
+ if (opmenu[opcode_index] == trans->opcode)
+ break;
+ }
+
+ if (opcode_index == cntlr.menubytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
+ trans->opcode);
+ return -1;
+ }
+
+ optypes = readw_(cntlr.optype);
+ optype = (optypes >> (opcode_index * 2)) & 0x3;
+ if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
+ optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
+ trans->bytesout >= 3) {
+ /* We guessed wrong earlier. Fix it up. */
+ trans->type = optype;
+ }
+ if (optype != trans->type) {
+ printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
+ optype);
+ return -1;
+ }
+ return opcode_index;
}
static int spi_setup_offset(spi_transaction *trans)
@@ -489,9 +489,11 @@
writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
spi_setup_type(&trans);
- if ((opcode_index = spi_setup_opcode(&trans)) < 0)
+ opcode_index = spi_setup_opcode(&trans);
+ if (opcode_index < 0)
return -1;
- if ((with_address = spi_setup_offset(&trans)) < 0)
+ with_address = spi_setup_offset(&trans);
+ if (with_address < 0)
return -1;
if (trans.opcode == SPI_OPCODE_WREN) {
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index f0c1ef2..f46f5ea 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -256,9 +256,8 @@
static void mc_read_map_entries(device_t dev, uint64_t *values)
{
int i;
- for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ for (i = 0; i < NUM_MAP_ENTRIES; i++)
read_map_entry(dev, &memory_map[i], &values[i]);
- }
}
static void mc_report_map_entries(device_t dev, uint64_t *values)
--
To view, visit https://review.coreboot.org/18884
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
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