[coreboot-gerrit] Change in coreboot[master]: arch/x86: Wrap lines at 80 columns
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 03:18:28 CET 2017
Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/18864 )
Change subject: arch/x86: Wrap lines at 80 columns
......................................................................
arch/x86: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
Reviewed-on: https://review.coreboot.org/18864
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/arch/x86/acpi.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/acpigen.c
M src/arch/x86/boot.c
M src/arch/x86/c_start.S
M src/arch/x86/cbmem.c
M src/arch/x86/exception.c
M src/arch/x86/id.S
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/acpigen.h
M src/arch/x86/include/arch/bootblock_romcc.h
M src/arch/x86/include/arch/cbfs.h
M src/arch/x86/include/arch/interrupt.h
M src/arch/x86/include/arch/io.h
M src/arch/x86/include/arch/pirq_routing.h
M src/arch/x86/include/arch/smp/mpspec.h
M src/arch/x86/memset.c
M src/arch/x86/mpspec.c
M src/arch/x86/pci_ops_conf1.c
M src/arch/x86/pci_ops_mmconf.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/smbios.c
M src/arch/x86/tables.c
M src/arch/x86/walkcbfs.S
24 files changed, 352 insertions(+), 180 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index eeab3b3..5227bd2 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -6,7 +6,8 @@
*
* Copyright (C) 2004 SUSE LINUX AG
* Copyright (C) 2005-2009 coresystems GmbH
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2016 Siemens AG
*
* ACPI FADT, FACS, and DSDT table support added by
@@ -589,7 +590,8 @@
void acpi_create_vfct(struct device *device,
struct acpi_vfct *vfct,
- unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current))
+ unsigned long (*acpi_fill_vfct)(struct device *device,
+ struct acpi_vfct *vfct_struct, unsigned long current))
{
acpi_header_t *header = &(vfct->header);
unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct);
@@ -613,7 +615,8 @@
}
void acpi_create_ivrs(acpi_ivrs_t *ivrs,
- unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current))
+ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
+ unsigned long current))
{
acpi_header_t *header = &(ivrs->header);
unsigned long current = (unsigned long)ivrs + sizeof(acpi_ivrs_t);
@@ -636,7 +639,8 @@
header->checksum = acpi_checksum((void *)ivrs, header->length);
}
-unsigned long acpi_write_hpet(device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+unsigned long acpi_write_hpet(device_t device, unsigned long current,
+ acpi_rsdp_t *rsdp)
{
acpi_hpet_t *hpet;
@@ -737,7 +741,8 @@
rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
}
-unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len)
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
+ acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len)
{
acpi_header_t *header = &(hest->header);
acpi_hest_hen_t *hen;
@@ -765,7 +770,7 @@
memset(pos, 0, sizeof(acpi_hest_hen_t));
hen->type = 3; /* SCI? */
hen->length = sizeof(acpi_hest_hen_t);
- hen->conf_we = 0; /* Configuration Write Enable. */
+ hen->conf_we = 0; /* Configuration Write Enable. */
hen->poll_interval = 0;
hen->vector = 0;
hen->sw2poll_threshold_val = 0;
@@ -1024,7 +1029,8 @@
for (dev = all_devices; dev; dev = dev->next) {
if (dev->ops && dev->ops->write_acpi_tables) {
- current = dev->ops->write_acpi_tables(dev, current, rsdp);
+ current = dev->ops->write_acpi_tables(dev, current,
+ rsdp);
current = acpi_align_current(current);
}
}
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ea04029..8549f63 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -105,7 +105,8 @@
/* Allocate backup with room for header. */
if (!backup_mem) {
- size_t header_sz = ALIGN_UP(sizeof(*backup_mem), BACKUP_PAGE_SZ);
+ size_t header_sz = ALIGN_UP(sizeof(*backup_mem),
+ BACKUP_PAGE_SZ);
backup_mem = cbmem_add(CBMEM_ID_RESUME, header_sz + size);
if (!backup_mem)
return -1;
@@ -126,7 +127,8 @@
if (!backup_mem)
return NULL;
- if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size, BACKUP_PAGE_SZ))
+ if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size,
+ BACKUP_PAGE_SZ))
return NULL;
if (backup_create_or_update(backup_mem, base, size) < 0)
@@ -158,7 +160,8 @@
/* Back up the OS-controlled memory where ramstage will be loaded. */
memcpy((void *)(uintptr_t)backup_mem->cbmem,
- (void *)(uintptr_t)backup_mem->lowmem, (size_t)backup_mem->size);
+ (void *)(uintptr_t)backup_mem->lowmem,
+ (size_t)backup_mem->size);
backup_mem->valid = 1;
}
@@ -175,7 +178,8 @@
/* Back up the OS-controlled memory where ramstage will be loaded. */
memcpy((void *)(uintptr_t)backup_mem->cbmem,
- (void *)(uintptr_t)backup_mem->lowmem, (size_t)backup_mem->size);
+ (void *)(uintptr_t)backup_mem->lowmem,
+ (size_t)backup_mem->size);
backup_mem->valid = 1;
}
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index 7e4775c..cbd0b5f 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2009 Rudolf Marek <r.marek at assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
@@ -494,12 +495,18 @@
})
*/
static char stream[] = {
- 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */
- 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */
- 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */
- 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */
+ /* 00000030 "0._PCT.," */
+ 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C,
+ /* 00000038 "........" */
+ 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00,
+ /* 00000040 "........" */
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000048 "....y..." */
+ 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14,
+ /* 00000050 "........" */
+ 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00,
+ /* 00000058 "........" */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x79, 0x00
};
acpigen_emit_stream(stream, ARRAY_SIZE(stream));
@@ -713,7 +720,8 @@
acpigen_pop_len();
}
-void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index)
+void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
+ u32 index)
{
acpigen_write_name("_CSD");
acpigen_write_package(1);
diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
index b9e6ee9..2e1becf 100644
--- a/src/arch/x86/boot.c
+++ b/src/arch/x86/boot.c
@@ -132,9 +132,13 @@
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
- /* Adjust the stack pointer to point into the new coreboot image */
+ /* Adjust the stack pointer to point into the new coreboot
+ * image
+ */
" addl 20(%%esp), %%esp\n\t"
- /* Adjust the instruction pointer to point into the new coreboot image */
+ /* Adjust the instruction pointer to point into the new coreboot
+ * image
+ */
" movl $1f, %%eax\n\t"
" addl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
@@ -166,10 +170,14 @@
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
- /* Adjust the stack pointer to point into the old coreboot image */
+ /* Adjust the stack pointer to point into the old coreboot
+ * image
+ */
" subl 20(%%esp), %%esp\n\t"
- /* Adjust the instruction pointer to point into the old coreboot image */
+ /* Adjust the instruction pointer to point into the old coreboot
+ * image
+ */
" movl $1f, %%eax\n\t"
" subl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 9a64fa6..29d3a53 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -349,7 +349,9 @@
/* selgdt 0x10, flat code segment */
.word 0xffff, 0x0000
- .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
/* selgdt 0x18, flat data segment */
.word 0xffff, 0x0000
@@ -377,11 +379,15 @@
/* selgdt 0x38, flat data segment 16 bit */
.word 0x0000, 0x0000 /* dummy */
- .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
/* selgdt 0x40, flat code segment 16 bit */
.word 0xffff, 0x0000
- .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
+ .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
#ifdef __x86_64__
/* selgdt 0x48, flat x64 code segment */
@@ -407,14 +413,16 @@
# use iret to jump to a 64-bit offset in a new code segment
# iret will pop cs:rip, flags, then ss:rsp
mov %ss, %ax # need to push ss..
- push %rax # push ss instuction not valid in x64 mode, so use ax
+ push %rax # push ss instuction not valid in x64 mode,
+ # so use ax
push %rsp
pushfq
push %rcx # cx is code segment selector from caller
mov $setCodeSelectorLongJump, %rax
push %rax
- # the iret will continue at next instruction, with the new cs value loaded
+ # the iret will continue at next instruction, with the new cs value
+ # loaded
iretq
setCodeSelectorLongJump:
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 6bbc18c..578bb8a 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -21,7 +21,8 @@
#if !defined(__PRE_RAM__)
void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
{
- /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */
+ /* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
+ */
}
static void *ramtop_pointer;
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 65bd33e..b8b0f3f 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -316,7 +316,9 @@
/* Wishlit implement a timeout in get_packet */
do {
- /* wait around for the start character, ignore all other characters */
+ /* wait around for the start character, ignore all other
+ * characters
+ */
while ((ch = (stub_getc() & 0x7f)) != '$');
checksum = 0;
xmitcsum = -1;
@@ -417,10 +419,12 @@
out_buffer[3] = '\0';
break;
case 'g': /* return the value of the CPU registers */
- copy_to_hex(out_buffer, &gdb_stub_registers, sizeof(gdb_stub_registers));
+ copy_to_hex(out_buffer, &gdb_stub_registers,
+ sizeof(gdb_stub_registers));
break;
case 'G': /* set the value of the CPU registers - return OK */
- copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers));
+ copy_from_hex(&gdb_stub_registers, in_buffer + 1,
+ sizeof(gdb_stub_registers));
memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t));
info->eip = gdb_stub_registers[PC];
info->cs = gdb_stub_registers[CS];
@@ -438,7 +442,9 @@
memcpy(out_buffer, "E01", 4);
break;
case 'M':
- /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
+ /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA
+ * return OK
+ */
ptr = &in_buffer[1];
if (parse_ulong(&ptr, &addr) &&
(*(ptr++) == ',') &&
@@ -451,8 +457,9 @@
break;
case 's':
case 'c':
- /* cAA..AA Continue at address AA..AA(optional) */
- /* sAA..AA Step one instruction from AA..AA(optional) */
+ /* cAA..AA Continue at address AA..AA(optional)
+ * sAA..AA Step one instruction from AA..AA(optional)
+ */
ptr = &in_buffer[1];
if (parse_ulong(&ptr, &addr))
info->eip = addr;
diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S
index f10aa08..6151990 100644
--- a/src/arch/x86/id.S
+++ b/src/arch/x86/id.S
@@ -23,9 +23,15 @@
.asciz CONFIG_MAINBOARD_VENDOR
part:
.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the
+ *vendor id
+ */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the
+ * vendor id
+ */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the
+ * part number
+ */
.long CONFIG_ROM_SIZE /* Size of this romimage */
.globl __id_end
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 41c4fa7..95cd3ac 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -4,7 +4,8 @@
* Copyright (C) 2004 SUSE LINUX AG
* Copyright (C) 2004 Nick Barker
* Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2016 Siemens AG
* (Written by Stefan Reinauer <stepan at coresystems.de>)
*
@@ -85,8 +86,9 @@
u8 bit_width; /* Register size in bits */
u8 bit_offset; /* Register bit offset */
union {
- u8 resv; /* Reserved in ACPI 2.0 - 2.0b */
- u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0 */
+ u8 resv; /* Reserved in ACPI 2.0 - 2.0b */
+ u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0
+ */
};
u32 addrl; /* Register address, low 32 bits */
u32 addrh; /* Register address, high 32 bits */
@@ -109,7 +111,7 @@
/* 0xc0-0xff: OEM defined */
/* Access size definitions for Generic address structure */
-#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */
+#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */
#define ACPI_ACCESS_SIZE_BYTE_ACCESS 1
#define ACPI_ACCESS_SIZE_WORD_ACCESS 2
#define ACPI_ACCESS_SIZE_DWORD_ACCESS 3
@@ -206,7 +208,9 @@
u32 length_low; /* Mem range length, low */
u32 length_high; /* Mem range length, high */
u32 resv1;
- u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, other bits reserved to 0 */
+ u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2,
+ * other bits reserved to 0
+ */
u32 resv2[2];
} __attribute__ ((packed)) acpi_srat_mem_t;
@@ -551,7 +555,9 @@
u16 resv;
u8 flags;
u8 enabled;
- u32 prealloc_erecords; /* The number of error records to pre-allocate for this error source. */
+ u32 prealloc_erecords; /* The number of error records to
+ * pre-allocate for this error source.
+ */
u32 max_section_per_record;
} __attribute__ ((packed)) acpi_hest_esd_t;
@@ -635,11 +641,13 @@
unsigned long current));
void acpi_create_ivrs(acpi_ivrs_t *ivrs,
- unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current));
+ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
+ unsigned long current));
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
void acpi_create_hpet(acpi_hpet_t *hpet);
-unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);
+unsigned long acpi_write_hpet(device_t device, unsigned long start,
+ acpi_rsdp_t *rsdp);
/* cpu/intel/speedstep/acpi.c */
void generate_cpu_entries(device_t device);
@@ -670,7 +678,8 @@
void acpi_write_hest(acpi_hest_t *hest,
unsigned long (*acpi_fill_hest)(acpi_hest_t *hest));
-unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
+ acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
void acpi_save_gnvs(u32 gnvs_address);
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index c70e4b9..b08ce93 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -2,7 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Rudolf Marek <r.marek at assembler.cz>
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -203,14 +204,15 @@
void acpigen_write_PRW(u32 wake, u32 level);
void acpigen_write_STA(uint8_t status);
void acpigen_write_TPC(const char *gnvs_tpc_limit);
-void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
- u32 control, u32 status);
+void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
+ u32 busmLat, u32 control, u32 status);
typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord;
void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
void acpigen_write_CST_package_entry(acpi_cstate_t *cstate);
void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries);
typedef enum { CSD_HW_ALL = 0xfe } CSD_coord;
-void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index);
+void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
+ u32 index);
void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
index 2e96d2a..d6962d6 100644
--- a/src/arch/x86/include/arch/bootblock_romcc.h
+++ b/src/arch/x86/include/arch/bootblock_romcc.h
@@ -49,8 +49,10 @@
#if CONFIG_USE_OPTION_TABLE
static void sanitize_cmos(void)
{
- if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
- unsigned char *cmos_default = (unsigned char *)walkcbfs("cmos.default");
+ if (cmos_error() || !cmos_chksum_valid()
+ || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) {
+ unsigned char *cmos_default =
+ (unsigned char *)walkcbfs("cmos.default");
if (cmos_default) {
int i;
cmos_disable_rtc();
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index 81100a5..54f0fa9 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -27,7 +27,8 @@
asm volatile (
"mov $1f, %%esp\n\t"
"jmp walkcbfs_asm\n\t"
- "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
+ "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi",
+ "esp");
return entry;
}
@@ -41,7 +42,9 @@
return (void *)0;
}
-/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */
+/* just enough to support findstage. copied because the original version doesn't
+ * easily pass through romcc
+ */
struct cbfs_stage_restricted {
unsigned long compression;
unsigned long entry; // this is really 64bit, but properly endianized
diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h
index a3c1b3d..90a29af 100644
--- a/src/arch/x86/include/arch/interrupt.h
+++ b/src/arch/x86/include/arch/interrupt.h
@@ -26,7 +26,8 @@
#elif CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <device/oprom/yabel/biosemu.h>
#else
-static inline void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { }
+static inline void mainboard_interrupt_handlers(int intXX,
+ int (*intXX_func)(void)) { }
#endif
#endif /* INTERRUPT_H */
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index f16c091..c194379 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -156,32 +156,38 @@
);
}
-static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
+static inline __attribute__((always_inline)) uint8_t read8(
+ const volatile void *addr)
{
return *((volatile uint8_t *)(addr));
}
-static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
+static inline __attribute__((always_inline)) uint16_t read16(
+ const volatile void *addr)
{
return *((volatile uint16_t *)(addr));
}
-static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
+static inline __attribute__((always_inline)) uint32_t read32(
+ const volatile void *addr)
{
return *((volatile uint32_t *)(addr));
}
-static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(volatile void *addr,
+ uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(volatile void *addr,
+ uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(volatile void *addr,
+ uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
@@ -238,8 +244,8 @@
/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 device_t;
-/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
- * We don't need to set %fs, and %gs anymore
+/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write
+ * memory above 4G, We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/
@@ -301,7 +307,8 @@
}
#define PCI_DEV_INVALID (0xffffffffU)
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev)
+static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id,
+ pci_devfn_t dev)
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
@@ -312,7 +319,8 @@
return PCI_DEV_INVALID;
}
-static inline pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+static inline pci_devfn_t pci_locate_device(unsigned int pci_id,
+ pci_devfn_t dev)
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
@@ -341,14 +349,16 @@
}
/* Generic functions for pnp devices */
-static inline __attribute__((always_inline)) void pnp_write_config(pnp_devfn_t dev, uint8_t reg, uint8_t value)
+static inline __attribute__((always_inline)) void pnp_write_config(
+ pnp_devfn_t dev, uint8_t reg, uint8_t value)
{
unsigned int port = dev >> 8;
outb(reg, port);
outb(value, port + 1);
}
-static inline __attribute__((always_inline)) uint8_t pnp_read_config(pnp_devfn_t dev, uint8_t reg)
+static inline __attribute__((always_inline)) uint8_t pnp_read_config(
+ pnp_devfn_t dev, uint8_t reg)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -384,7 +394,8 @@
static inline __attribute__((always_inline))
uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned int index)
{
- return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1);
+ return ((uint16_t)(pnp_read_config(dev, index)) << 8)
+ | pnp_read_config(dev, index + 1);
}
static inline __attribute__((always_inline))
diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
index d1390ba..acd456b 100644
--- a/src/arch/x86/include/arch/pirq_routing.h
+++ b/src/arch/x86/include/arch/pirq_routing.h
@@ -56,7 +56,8 @@
struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
} __attribute__((packed));
-unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table);
+unsigned long copy_pirq_routing_table(unsigned long addr,
+ const struct irq_routing_table *routing_table);
unsigned long write_pirq_routing_table(unsigned long start);
#if CONFIG_PIRQ_ROUTE
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 4123e74..4c80dbb 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -278,8 +278,10 @@
unsigned long write_smp_table(unsigned long addr);
void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa);
-void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external);
-void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus);
+void mptable_add_isa_interrupts(struct mp_config_table *mc,
+ unsigned long bus_isa, unsigned long apicid, int external);
+void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
+ int *isa_bus);
void *mptable_finalize(struct mp_config_table *mc);
#endif
diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c
index c87a3b3..b536e68 100644
--- a/src/arch/x86/memset.c
+++ b/src/arch/x86/memset.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation,
+ * Inc.
* This file is part of the GNU C Library.
*
* This program is free software; you can redistribute it and/or
diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c
index b0d563a..ab0514b 100644
--- a/src/arch/x86/mpspec.c
+++ b/src/arch/x86/mpspec.c
@@ -68,7 +68,8 @@
return checksum;
}
-static void *smp_write_floating_table_physaddr(uintptr_t addr, uintptr_t mpf_physptr, unsigned int virtualwire)
+static void *smp_write_floating_table_physaddr(uintptr_t addr,
+ uintptr_t mpf_physptr, unsigned int virtualwire)
{
struct intel_mp_floating *mf;
void *v;
@@ -96,7 +97,8 @@
{
/* 16 byte align the table address */
addr = (addr + 0xf) & (~0xf);
- return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN, virtualwire);
+ return smp_write_floating_table_physaddr(addr, addr
+ + SMP_FLOATING_TABLE_LEN, virtualwire);
}
void *smp_next_mpc_entry(struct mp_config_table *mc)
@@ -173,7 +175,8 @@
for (cpu = all_devices; cpu; cpu = cpu->next) {
unsigned long cpu_flag;
if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
+ (cpu->bus->dev->path.type !=
+ DEVICE_PATH_CPU_CLUSTER))
continue;
if (!cpu->enabled)
@@ -182,12 +185,14 @@
cpu_flag = MPC_CPU_ENABLED;
if (boot_apic_id == cpu->path.apic.apic_id)
- cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+ cpu_flag = MPC_CPU_ENABLED
+ | MPC_CPU_BOOTPROCESSOR;
if (cpu->path.apic.apic_id == order_id) {
smp_write_processor(mc,
cpu->path.apic.apic_id, apic_version,
- cpu_flag, cpu_features, cpu_feature_flags
+ cpu_flag, cpu_features,
+ cpu_feature_flags
);
break;
}
@@ -252,7 +257,8 @@
mpc->mpc_dstirq = dstirq;
smp_add_mpc_entry(mc, sizeof(*mpc));
#ifdef DEBUG_MPTABLE
- printk(BIOS_DEBUG, "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
+ printk(BIOS_DEBUG,
+ "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
srcbus, srcbusirq, dstapic, dstirq);
hexdump(__func__, mpc, sizeof(*mpc));
#endif
@@ -272,9 +278,11 @@
u8 dstapic, u8 dstirq)
{
u8 srcbusirq = (dev << 2) | pirq;
- printk(BIOS_SPEW, "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n", srcbusirq, dev, pirq);
- smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, srcbus,
- srcbusirq, dstapic, dstirq);
+ printk(BIOS_SPEW,
+ "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n",
+ srcbusirq, dev, pirq);
+ smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL
+ | MP_IRQ_POLARITY_LOW, srcbus, srcbusirq, dstapic, dstirq);
}
void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
@@ -306,9 +314,12 @@
if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
/* pci device */
- printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child));
+ printk(BIOS_DEBUG, "route irq: %s\n",
+ dev_path(child));
for (i = 0; i < 4; i++)
- smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]);
+ smp_write_intsrc(mc, irqtype, irqflag,
+ srcbus, (slot<<2)|i, dstapic,
+ dstirq_x[i]);
goto next;
}
@@ -316,8 +327,10 @@
case PCI_CLASS_BRIDGE_PCI:
case PCI_CLASS_BRIDGE_PCMCIA:
case PCI_CLASS_BRIDGE_CARDBUS:
- printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child));
- smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x);
+ printk(BIOS_DEBUG, "route irq bridge: %s\n",
+ dev_path(child));
+ smp_write_intsrc_pci_bridge(mc, irqtype,
+ irqflag, child, dstapic, dstirq_x);
}
next:
@@ -416,30 +429,49 @@
void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
{
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE
+ | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE
+ | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
}
-void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external_int2)
+void mptable_add_isa_interrupts(struct mp_config_table *mc,
+ unsigned long bus_isa, unsigned long apicid, int external_int2)
{
-/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+/*I/O Ints: Type Trigger Polarity
+ * Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT,
- MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid, 0x1);
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x0, apicid, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x1, apicid, 0x1);
smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT,
- MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, apicid, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, apicid, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid, 0xf);
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x0, apicid, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x3, apicid, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x4, apicid, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x6, apicid, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x7, apicid, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x8, apicid, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x9, apicid, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xa, apicid, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xb, apicid, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xc, apicid, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xd, apicid, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xe, apicid, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0xf, apicid, 0xf);
}
void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
@@ -460,7 +492,8 @@
struct bus *bus;
for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->secondary > 255) {
- printk(BIOS_ERR, "A bus claims to have a bus ID > 255?!? Aborting");
+ printk(BIOS_ERR,
+ "A bus claims to have a bus ID > 255?!? Aborting");
return;
}
buses[bus->secondary] = 1;
@@ -479,9 +512,11 @@
void *mptable_finalize(struct mp_config_table *mc)
{
- mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+ mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
@@ -495,6 +530,7 @@
struct device *oldparent;
void *tmp, *v;
int isaioapic = -1, have_fixed_entries;
+ struct pci_irq_info *pci_irq_info;
v = smp_write_floating_table(addr, 0);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -510,7 +546,8 @@
continue;
if (!(ioapic_config = dev->chip_info)) {
- printk(BIOS_ERR, "%s has no config, ignoring\n", dev_path(dev));
+ printk(BIOS_ERR, "%s has no config, ignoring\n",
+ dev_path(dev));
continue;
}
smp_write_ioapic(mc, dev->path.ioapic.ioapic_id,
@@ -519,7 +556,8 @@
if (ioapic_config->have_isa_interrupts) {
if (isaioapic >= 0)
- printk(BIOS_ERR, "More than one IOAPIC with ISA interrupts?\n");
+ printk(BIOS_ERR,
+ "More than one IOAPIC with ISA interrupts?\n");
else
isaioapic = dev->path.ioapic.ioapic_id;
}
@@ -539,16 +577,19 @@
have_fixed_entries = 0;
for (pin = 0; pin < 4; pin++) {
if (dev->pci_irq_info[pin].ioapic_dst_id) {
- printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev),
+ printk(BIOS_DEBUG,
+ "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n",
+ dev_path(dev),
pin + 'A',
dev->pci_irq_info[pin].ioapic_dst_id,
dev->pci_irq_info[pin].ioapic_irq_pin);
smp_write_intsrc(mc, mp_INT,
- dev->pci_irq_info[pin].ioapic_flags,
- dev->bus->secondary,
- ((dev->path.pci.devfn & 0xf8) >> 1) | pin,
- dev->pci_irq_info[pin].ioapic_dst_id,
- dev->pci_irq_info[pin].ioapic_irq_pin);
+ dev->pci_irq_info[pin].ioapic_flags,
+ dev->bus->secondary,
+ ((dev->path.pci.devfn & 0xf8) >> 1)
+ | pin,
+ dev->pci_irq_info[pin].ioapic_dst_id,
+ dev->pci_irq_info[pin].ioapic_irq_pin);
have_fixed_entries = 1;
}
}
@@ -557,28 +598,34 @@
pin = (dev->path.pci.devfn & 7) % 4;
oldparent = parent = dev;
while ((parent = parent->bus->dev)) {
- parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7);
+ parentpin = (oldparent->path.pci.devfn >> 3)
+ + (oldparent->path.pci.devfn & 7);
parentpin += dev->path.pci.devfn & 7;
parentpin += dev->path.pci.devfn >> 3;
parentpin %= 4;
- if (parent->pci_irq_info[parentpin].ioapic_dst_id) {
- printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n",
+ pci_irq_info = &parent->pci_irq_info[parentpin];
+ if (pci_irq_info->ioapic_dst_id) {
+ printk(BIOS_DEBUG,
+ "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n",
dev_path(dev), pin + 'A',
- parent->pci_irq_info[parentpin].ioapic_dst_id,
- parent->pci_irq_info[parentpin].ioapic_irq_pin);
+ pci_irq_info->ioapic_dst_id,
+ pci_irq_info->ioapic_irq_pin);
smp_write_intsrc(mc, mp_INT,
- parent->pci_irq_info[parentpin].ioapic_flags,
- dev->bus->secondary,
- ((dev->path.pci.devfn & 0xf8) >> 1) | pin,
- parent->pci_irq_info[parentpin].ioapic_dst_id,
- parent->pci_irq_info[parentpin].ioapic_irq_pin);
+ pci_irq_info->ioapic_flags,
+ dev->bus->secondary,
+ ((dev->path.pci.devfn & 0xf8)
+ >> 1) | pin,
+ pci_irq_info->ioapic_dst_id,
+ pci_irq_info->ioapic_irq_pin);
break;
}
if (parent->path.type == DEVICE_PATH_DOMAIN) {
- printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev));
+ printk(BIOS_WARNING,
+ "no IRQ found for %s\n",
+ dev_path(dev));
break;
}
oldparent = parent;
diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
index 61d1d96..820744c 100644
--- a/src/arch/x86/pci_ops_conf1.c
+++ b/src/arch/x86/pci_ops_conf1.c
@@ -22,11 +22,11 @@
#if !CONFIG_PCI_IO_CFG_EXT
#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \
- (devfn << 8) | (where & ~3))
+ (devfn << 8) | (where & ~3))
#else
#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \
- (devfn << 8) | ((where & 0xff) & ~3) |\
- ((where & 0xf00)<<16))
+ (devfn << 8) | ((where & 0xff) & ~3) |\
+ ((where & 0xf00)<<16))
#endif
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn,
diff --git a/src/arch/x86/pci_ops_mmconf.c b/src/arch/x86/pci_ops_mmconf.c
index 989c580..cf08e17 100644
--- a/src/arch/x86/pci_ops_mmconf.c
+++ b/src/arch/x86/pci_ops_mmconf.c
@@ -22,10 +22,10 @@
*/
#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
- ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\
- (((SEGBUS) & 0xFFF) << 20) |\
- (((DEVFN) & 0xFF) << 12) |\
- ((WHERE) & 0xFFF)) & ~MASK))
+ ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\
+ (((SEGBUS) & 0xFFF) << 20) |\
+ (((DEVFN) & 0xFF) << 12) |\
+ ((WHERE) & 0xFFF)) & ~MASK))
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where)
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c
index e844513..405dad0 100644
--- a/src/arch/x86/pirq_routing.c
+++ b/src/arch/x86/pirq_routing.c
@@ -29,10 +29,10 @@
printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n");
if (sizeof(struct irq_routing_table) != rt->size) {
- printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
- (unsigned int) sizeof(struct irq_routing_table),
- rt->size
- );
+ printk(BIOS_WARNING,
+ "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
+ (unsigned int) sizeof(struct irq_routing_table),
+ rt->size);
rt->size = sizeof(struct irq_routing_table);
}
@@ -46,8 +46,9 @@
sum = rt->checksum - sum;
if (sum != rt->checksum) {
- printk(BIOS_WARNING, "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n",
- rt->checksum, sum);
+ printk(BIOS_WARNING,
+ "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n",
+ rt->checksum, sum);
rt->checksum = sum;
}
@@ -73,14 +74,17 @@
printk(BIOS_INFO, "done.\n");
}
-static int verify_copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table)
+static int verify_copy_pirq_routing_table(unsigned long addr,
+ const struct irq_routing_table *routing_table)
{
int i;
uint8_t *rt_orig, *rt_curr;
rt_curr = (uint8_t *)addr;
rt_orig = (uint8_t *)routing_table;
- printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08lx... ", addr);
+ printk(BIOS_INFO,
+ "Verifying copy of Interrupt Routing Table at 0x%08lx... ",
+ addr);
for (i = 0; i < routing_table->size; i++) {
if (*(rt_curr + i) != *(rt_orig + i)) {
printk(BIOS_INFO, "failed\n");
@@ -183,13 +187,15 @@
}
#endif
-unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table)
+unsigned long copy_pirq_routing_table(unsigned long addr,
+ const struct irq_routing_table *routing_table)
{
/* Align the table to be 16 byte aligned. */
addr = ALIGN(addr, 16);
/* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ", addr);
+ printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ",
+ addr);
memcpy((void *)addr, routing_table, routing_table->size);
printk(BIOS_INFO, "done.\n");
#if CONFIG_DEBUG_PIRQ
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 9276fc2..6244327 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
*
* This program is free software; you can redistribute it and/or
@@ -124,7 +125,8 @@
}
/* this function will fill the corresponding manufacturer */
-void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t)
+void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id,
+ struct smbios_type17 *t)
{
switch (mod_id) {
case 0x2c80:
@@ -280,7 +282,8 @@
#if !CONFIG_CHROMEOS
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
- t->bios_version = smbios_add_string(t->eos, smbios_mainboard_bios_version());
+ t->bios_version = smbios_add_string(t->eos,
+ smbios_mainboard_bios_version());
#else
#define SPACES \
" "
@@ -371,9 +374,12 @@
t->type = SMBIOS_SYSTEM_INFORMATION;
t->handle = handle;
t->length = len - 2;
- t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer());
- t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name());
- t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number());
+ t->manufacturer = smbios_add_string(t->eos,
+ smbios_mainboard_manufacturer());
+ t->product_name = smbios_add_string(t->eos,
+ smbios_mainboard_product_name());
+ t->serial_number = smbios_add_string(t->eos,
+ smbios_mainboard_serial_number());
t->sku = smbios_add_string(t->eos, smbios_mainboard_sku());
t->version = smbios_add_string(t->eos, smbios_mainboard_version());
#ifdef CONFIG_MAINBOARD_FAMILY
@@ -394,9 +400,12 @@
t->type = SMBIOS_BOARD_INFORMATION;
t->handle = handle;
t->length = len - 2;
- t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer());
- t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name());
- t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number());
+ t->manufacturer = smbios_add_string(t->eos,
+ smbios_mainboard_manufacturer());
+ t->product_name = smbios_add_string(t->eos,
+ smbios_mainboard_product_name());
+ t->serial_number = smbios_add_string(t->eos,
+ smbios_mainboard_serial_number());
t->version = smbios_add_string(t->eos, smbios_mainboard_version());
len = t->length + smbios_string_table_len(t->eos);
*current += len;
@@ -412,7 +421,8 @@
t->type = SMBIOS_SYSTEM_ENCLOSURE;
t->handle = handle;
t->length = len - 2;
- t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer());
+ t->manufacturer = smbios_add_string(t->eos,
+ smbios_mainboard_manufacturer());
t->bootup_state = SMBIOS_STATE_SAFE;
t->power_supply_state = SMBIOS_STATE_SAFE;
t->thermal_state = SMBIOS_STATE_SAFE;
@@ -500,7 +510,8 @@
return 0; /* can't find mem info in cbmem */
printk(BIOS_INFO, "Create SMBIOS type 17\n");
- for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
+ for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm);
+ i++) {
struct dimm_info *dimm;
dimm = &meminfo->dimm[i];
len = create_smbios_type17_for_dimm(dimm, current, handle);
@@ -562,7 +573,8 @@
return len;
}
-static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current)
+static int smbios_walk_device_tree(struct device *tree, int *handle,
+ unsigned long *current)
{
struct device *dev;
int len = 0;
@@ -600,21 +612,32 @@
current = ALIGN(current, 16);
tables = current;
- update_max(len, max_struct_size, smbios_write_type0(¤t, handle++));
- update_max(len, max_struct_size, smbios_write_type1(¤t, handle++));
- update_max(len, max_struct_size, smbios_write_type2(¤t, handle++));
- update_max(len, max_struct_size, smbios_write_type3(¤t, handle++));
- update_max(len, max_struct_size, smbios_write_type4(¤t, handle++));
- update_max(len, max_struct_size, smbios_write_type11(¤t, &handle));
+ update_max(len, max_struct_size, smbios_write_type0(¤t,
+ handle++));
+ update_max(len, max_struct_size, smbios_write_type1(¤t,
+ handle++));
+ update_max(len, max_struct_size, smbios_write_type2(¤t,
+ handle++));
+ update_max(len, max_struct_size, smbios_write_type3(¤t,
+ handle++));
+ update_max(len, max_struct_size, smbios_write_type4(¤t,
+ handle++));
+ update_max(len, max_struct_size, smbios_write_type11(¤t,
+ &handle));
#if CONFIG_ELOG
- update_max(len, max_struct_size, elog_smbios_write_type15(¤t, handle++));
+ update_max(len, max_struct_size, elog_smbios_write_type15(¤t,
+ handle++));
#endif
- update_max(len, max_struct_size, smbios_write_type17(¤t, &handle));
- update_max(len, max_struct_size, smbios_write_type32(¤t, handle++));
+ update_max(len, max_struct_size, smbios_write_type17(¤t,
+ &handle));
+ update_max(len, max_struct_size, smbios_write_type32(¤t,
+ handle++));
- update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, &handle, ¤t));
+ update_max(len, max_struct_size, smbios_walk_device_tree(all_devices,
+ &handle, ¤t));
- update_max(len, max_struct_size, smbios_write_type127(¤t, handle++));
+ update_max(len, max_struct_size, smbios_write_type127(¤t,
+ handle++));
memset(se, 0, sizeof(struct smbios_entry));
memcpy(se->anchor, "_SM_", 4);
@@ -629,7 +652,8 @@
se->struct_table_length = len;
se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10,
- sizeof(struct smbios_entry) - 0x10);
+ sizeof(struct smbios_entry)
+ - 0x10);
se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry));
return current;
}
diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index 93bd0dd..7b06550 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -41,10 +41,12 @@
/* And add a high table version for those payloads that
* want to live in the F segment
*/
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_PIRQ, MAX_PIRQ_TABLE_SIZE);
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_PIRQ,
+ MAX_PIRQ_TABLE_SIZE);
if (high_table_pointer) {
unsigned long new_high_table_pointer;
- new_high_table_pointer = write_pirq_routing_table(high_table_pointer);
+ new_high_table_pointer =
+ write_pirq_routing_table(high_table_pointer);
// FIXME make pirq table code intelligent enough to know how
// much space it's going to need.
if (new_high_table_pointer > (high_table_pointer
@@ -68,7 +70,8 @@
rom_table_end = write_smp_table(rom_table_end);
rom_table_end = ALIGN(rom_table_end, 1024);
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE, MAX_MP_TABLE_SIZE);
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE,
+ MAX_MP_TABLE_SIZE);
if (high_table_pointer) {
unsigned long new_high_table_pointer;
new_high_table_pointer = write_smp_table(high_table_pointer);
@@ -105,7 +108,8 @@
* coreboot table. This leaves us with 47KB for all of ACPI. Let's see
* how far we get.
*/
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI, MAX_ACPI_SIZE);
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI,
+ MAX_ACPI_SIZE);
if (high_table_pointer) {
unsigned long acpi_start = high_table_pointer;
unsigned long new_high_table_pointer;
@@ -139,7 +143,8 @@
writes longest size available. */
memcpy(low_rsdp, high_rsdp, sizeof(acpi_rsdp_t));
} else {
- printk(BIOS_ERR, "ERROR: Didn't find RSDP in high table.\n");
+ printk(BIOS_ERR,
+ "ERROR: Didn't find RSDP in high table.\n");
}
rom_table_end = ALIGN(rom_table_end + sizeof(acpi_rsdp_t), 16);
} else {
@@ -156,13 +161,16 @@
#define MAX_SMBIOS_SIZE 2048
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE);
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS,
+ MAX_SMBIOS_SIZE);
if (high_table_pointer) {
unsigned long new_high_table_pointer;
- new_high_table_pointer = smbios_write_tables(high_table_pointer);
+ new_high_table_pointer =
+ smbios_write_tables(high_table_pointer);
rom_table_end = ALIGN(rom_table_end, 16);
- memcpy((void *)rom_table_end, (void *)high_table_pointer, sizeof(struct smbios_entry));
+ memcpy((void *)rom_table_end, (void *)high_table_pointer,
+ sizeof(struct smbios_entry));
rom_table_end += sizeof(struct smbios_entry);
if (new_high_table_pointer > (high_table_pointer
@@ -171,8 +179,11 @@
printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);
} else {
- unsigned long new_rom_table_end = smbios_write_tables(rom_table_end);
- printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end);
+ unsigned long new_rom_table_end;
+
+ new_rom_table_end = smbios_write_tables(rom_table_end);
+ printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end
+ - rom_table_end);
rom_table_end = ALIGN(new_rom_table_end, 16);
}
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index bd71f19..ded6558 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -71,7 +71,9 @@
/* LARCHIVE header found */
mov %ebx, %edi
- add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after struct cbfs_file */
+ add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after
+ * struct cbfs_file
+ */
mov %eax, %ecx
repe cmpsb
/* zero flag set if strings are equal */
@@ -112,7 +114,9 @@
add $1, %ecx
cmp %ecx, %ebx
- /* if bootblockstart >= addr (==we're still in the data area) , jump back */
+ /* if bootblockstart >= addr (==we're still in the data area),
+ * jump back
+ */
jbe walker
out:
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins)
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