[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Add int to unsigned

[Lee Leahy (Code Review)]

Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/18870 )

Change subject: soc/intel/braswell: Add int to unsigned
......................................................................

soc/intel/braswell: Add int to unsigned

Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build for cyan

Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/spi.c
5 files changed, 9 insertions(+), 7 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/18870/1

diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 57590c2..4d7b906 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -339,7 +339,8 @@
 	.init = soc_init,
 };
 
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(device_t dev, unsigned int vendor,
+	unsigned int device)
 {
 	printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
 			__FILE__, __func__, dev_name(dev), vendor, device);
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 4662b43..40bda12 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -44,7 +44,7 @@
 #define FIRMWARE_REG_BASE_C0 0x144000
 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
 
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(device_t dev, u32 *field, unsigned int index)
 {
 	struct resource *res;
 
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index 1d70eb0..9ea154a 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -159,7 +159,8 @@
 	southcluster_enable_dev(dev);
 }
 
-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
+static void pcie_root_set_subsystem(device_t dev, unsigned int vid,
+	unsigned int did)
 {
 	printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
 			__FILE__, __func__, dev_name(dev), vid, did);
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 12bc930..4e4d157 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -330,7 +330,7 @@
 
 static int place_device_in_d3hot(device_t dev)
 {
-	unsigned offset;
+	unsigned int offset;
 
 	printk(BIOS_SPEW, "%s/%s ( %s )\n",
 			__FILE__, __func__, dev_name(dev));
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 86b3351..514e70e 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -90,7 +90,7 @@
 	uint16_t *optype;
 	uint32_t *addr;
 	uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
 	uint8_t *status;
 	uint16_t *control;
 } ich_spi_controller;
@@ -290,13 +290,13 @@
 	uint32_t offset;
 } spi_transaction;
 
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
 	trans->out += bytes;
 	trans->bytesout -= bytes;
 }
 
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
 	trans->in += bytes;
 	trans->bytesin -= bytes;

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>