[coreboot-gerrit] Change in coreboot[master]: google/veyron: Work around RAM code strapping error

[Julius Werner (Code Review)]

Hello Patrick Georgi,

I'd like you to do a code review.  Please visit

    https://review.coreboot.org/18859

to review the following change.


Change subject: google/veyron: Work around RAM code strapping error
......................................................................

google/veyron: Work around RAM code strapping error

With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.

BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.

Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/mainboard/google/veyron/Kconfig
M src/mainboard/google/veyron/boardid.c
2 files changed, 14 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/18859/1

diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index 0bd1e2e..2a16ff9 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -18,6 +18,16 @@
 
 if BOARD_GOOGLE_VEYRON
 
+# Some Veyron boards incorrectly had their RAM code strapped with 100Kohm
+# resistors. These get overpowered by the SoC's internal pull-downs, so we
+# cannot read those pins as tri-state. They're restricted to binary RAM codes.
+config VEYRON_FORCE_BINARY_RAM_CODE
+	bool
+	default y if BOARD_GOOGLE_VEYRON_JAQ
+	default y if BOARD_GOOGLE_VEYRON_JERRY
+	default y if BOARD_GOOGLE_VEYRON_MIGHTY
+	default n
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ID_AUTO
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index 47e946e..8bd1d76 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -38,7 +38,10 @@
 	gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
 		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
 
-	code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
+	if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE))
+		code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+	else
+		code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
 	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
 
 	return code;

-- 
To view, visit https://review.coreboot.org/18859
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>