[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Use common car teardown common code

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18826

-gerrit

commit dd6000d225e2bb69a77716a5cbd45cd83a9b3ae8
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Mar 15 17:28:38 2017 +0530

    soc/intel/skylake: Use common car teardown common code
    
    Change-Id: I4f8b3360078612f53db63f2bd9021fe34137cd9c
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/drivers/intel/fsp1_1/after_raminit.S         |  4 +-
 src/soc/intel/skylake/include/soc/car_teardown.S | 54 ------------------------
 src/soc/intel/skylake/romstage/car_stage_fsp20.S |  3 +-
 3 files changed, 4 insertions(+), 57 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index 3a4116a..cd56ea8 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -32,8 +32,8 @@
 
 #if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
 
-	/* SOC specific NEM */
-	#include <soc/car_teardown.S>
+	/* chipset_teardown_car() is expected to disable cache-as-ram. */
+	call	chipset_teardown_car
 
 #else
 .extern fih_car
diff --git a/src/soc/intel/skylake/include/soc/car_teardown.S b/src/soc/intel/skylake/include/soc/car_teardown.S
deleted file mode 100644
index 315b3c1..0000000
--- a/src/soc/intel/skylake/include/soc/car_teardown.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-.equ		IA32_PQR_ASSOC,			0x0c8f
-
-	/* Disable MTRR by clearing the IA32_MTRR_DEF_TYPE MSR E flag. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	andl	$(~MTRR_DEF_TYPE_EN), %eax
-	wrmsr
-
-	/* Invalidate Cache */
-	invd
-
-	/*
-	 * Disable No-Eviction Mode Run State by clearing
-	 * NO_EVICT_MODE MSR 2E0h bit [1] = 0
-	 */
-	movl	$0x000002E0, %ecx
-	rdmsr
-	andl	$~(0x2), %eax
-	wrmsr
-
-	/*
-	 * Disable No-Eviction Mode Setup State by clearing
-	 * NO_EVICT_MODE MSR 2E0h bit [0] = 0
-	 */
-	rdmsr
-	andl	$~(0x1), %eax
-	wrmsr
-
-	/*
-	 * Set IA32_PQR_ASSOC = 0x00
-	 * This step guarantees that no protected way remain in LLC cache,
-	 * all the ways are open for the evictions.
-	 */
-	movl	$IA32_PQR_ASSOC, %ecx
-	movl	$0x00, %eax
-	xorl	%edx, %edx
-	wrmsr
diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S
index c6401fa..5ef8bd6 100644
--- a/src/soc/intel/skylake/romstage/car_stage_fsp20.S
+++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S
@@ -37,7 +37,8 @@ car_stage_entry:
 	/* Switch to the stack in RAM */
 	movl	%eax, %esp
 
-	#include <soc/car_teardown.S>
+	/* chipset_teardown_car() is expected to disable cache-as-ram. */
+	call	chipset_teardown_car
 
 	/* Display the MTRRs */
 	call	soc_display_mtrrs